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Tue, 30 May 2023 09:12:02 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v3 4/5] iommu/amd: Do not Invalidate IRT when IRTE caching is disabled Date: Tue, 30 May 2023 10:11:36 -0400 Message-ID: <20230530141137.14376-5-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230530141137.14376-1-suravee.suthikulpanit@amd.com> References: <20230530141137.14376-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT044:EE_|CY8PR12MB8214:EE_ X-MS-Office365-Filtering-Correlation-Id: 48e52a11-1585-450f-6627-08db6117d909 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oQyTcyWUg7+clYu6S7DQEesyA/PyrE6yL/PCtIOp6T0m9Bkh5asVuQwPTODWCpv9jrf0Azcg16fPbAFje3wqFnXct9sd+1i3PH2m79WHXuaSOzcxPZnLNykZOKwxsKFCeLKgXAzejqSB0NbKChyAtdyqy9srWi2BGF43eQ2r0i1Pf2ukqx2RkemNNx7u9K+DgtVND32CJ4ruvMBwR/csnTKbR0D0eTCeII09AE2y1DPIMfCZVvU8vK1xFDl12iQQOjTEUdy1WIMlmuHvLdUNi0Hlwq0JEqfPCeiV5UPtizH1CW9ek0RkrPgwCMmJpjuPs4yzRIglxuV/Lz0fN7NUNKkJswgbcx2OIpjjkYl00bUDsnsKes4g1mtmPEBL0e3kOnK8wAK5S6cwSGY3+OFQuYodle+wCCFxwgOD1D2sczmrl4sUxOwkj8SWweJomDlqcuQu9j+DDPjtPDgaiO9Fo1D+3Y15OugLarYZXxit9ugr/XMfPfm7IcwwiNIGXWZ9jhpd8c6Ev5wCiE93BvmzxMc518Jw6vyXSgHxSVjQ4q4jAzVQd8GjYNdd82xEP6qxkCH812QJ6BxxRwWFC7eKhCFTmd2CoXdgSDWbFXm+y/kzNdmNtFcJ8LttOgJuMrWE5V7zPRFSk2o9xyML9ngKkao/J24L3Rs0Syq1Zlt7aphmX4KGtc8NNMCVGY0VPDXx0CxLgYdEAdWa6k0iMU0U959OcRSXSter1hBmyhNVOJBfIFunM/pZKNgao60/LwgPpMMlfhaWNB+q1ZjIYhSddw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(396003)(346002)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(186003)(16526019)(2616005)(41300700001)(426003)(336012)(83380400001)(1076003)(36860700001)(26005)(7696005)(6666004)(47076005)(478600001)(110136005)(40460700003)(54906003)(356005)(81166007)(82740400003)(70206006)(4326008)(70586007)(40480700001)(316002)(5660300002)(8676002)(8936002)(44832011)(2906002)(86362001)(82310400005)(36756003)(36900700001);DIR:OUT;SFP:1101; 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Therefore, add logic to bypass the operation. Reviewed-by: Jerry Snitselaar Suggested-by: Joao Martins Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 0c4a2796bb0a..51c2b018433d 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1273,12 +1273,24 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) u32 devid; u16 last_bdf = iommu->pci_seg->last_bdf; + if (iommu->irtcachedis_enabled) + return; + for (devid = 0; devid <= last_bdf; devid++) iommu_flush_irt(iommu, devid); iommu_completion_wait(iommu); } +static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid) +{ + if (iommu->irtcachedis_enabled) + return; + + iommu_flush_irt(iommu, devid); + iommu_completion_wait(iommu); +} + void iommu_flush_all_caches(struct amd_iommu *iommu) { if (iommu_feature(iommu, FEATURE_IA)) { @@ -3028,8 +3040,7 @@ static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); return 0; } @@ -3048,8 +3059,7 @@ static int modify_irte(struct amd_iommu *iommu, table->table[index] = irte->val; raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); return 0; } @@ -3067,8 +3077,7 @@ static void free_irte(struct amd_iommu *iommu, u16 devid, int index) iommu->irte_ops->clear_allocated(table, index); raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); } static void irte_prepare(void *entry,