diff mbox series

phy: mediatek: hdmi: mt8195: fix prediv bad upper limit test

Message ID 20230529-hdmi_phy_fix-v1-1-bf65f53af533@baylibre.com
State New
Headers
Series phy: mediatek: hdmi: mt8195: fix prediv bad upper limit test |

Commit Message

Guillaume Ranquet May 30, 2023, 8:43 a.m. UTC 
  The pll prediv calculus searchs for the smallest prediv that gets
the ns_hdmipll_ck in the range of 5 GHz to 12 GHz.

A typo in the upper bound test was testing for 5Ghz to 1Ghz

Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
---
 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


---
base-commit: 9f925874281f7e8855855d6210d6e29d844e4307
change-id: 20230529-hdmi_phy_fix-9dab6eb42ef7

Best regards,

Comments

AngeloGioacchino Del Regno May 30, 2023, 9:24 a.m. UTC | #1 
Il 30/05/23 10:43, Guillaume Ranquet ha scritto:
> The pll prediv calculus searchs for the smallest prediv that gets
> the ns_hdmipll_ck in the range of 5 GHz to 12 GHz.
> 
> A typo in the upper bound test was testing for 5Ghz to 1Ghz
> 
> Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Vinod Koul July 11, 2023, 7:36 a.m. UTC | #2 
On Tue, 30 May 2023 10:43:07 +0200, Guillaume Ranquet wrote:
> The pll prediv calculus searchs for the smallest prediv that gets
> the ns_hdmipll_ck in the range of 5 GHz to 12 GHz.
> 
> A typo in the upper bound test was testing for 5Ghz to 1Ghz
> 
> 

Applied, thanks!

[1/1] phy: mediatek: hdmi: mt8195: fix prediv bad upper limit test
      commit: 059c78ebf1e94a825e27cc3ef8a9d77cef06827e

Best regards,
diff mbox series

Patch

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index 8aa7251de4a9..bbfe11d6a69d 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -253,7 +253,7 @@  static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
 	for (i = 0; i < ARRAY_SIZE(txpredivs); i++) {
 		ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i];
 		if (ns_hdmipll_ck >= 5 * GIGA &&
-		    ns_hdmipll_ck <= 1 * GIGA)
+		    ns_hdmipll_ck <= 12 * GIGA)
 			break;
 	}
 	if (i == (ARRAY_SIZE(txpredivs) - 1) &&