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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by AS8PR04MB8070.eurprd04.prod.outlook.com (2603:10a6:20b:3f2::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.18; Fri, 26 May 2023 14:37:17 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::25d3:de2:ef1:3884]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::25d3:de2:ef1:3884%4]) with mapi id 15.20.6411.028; Fri, 26 May 2023 14:37:17 +0000 From: Frank Li To: vkoul@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, peng.fan@nxp.com, joy.zou@nxp.com, shenwei.wang@nxp.com, imx@lists.linux.dev Subject: [PATCH v1 07/12] dmaengine: fsl-edma: refactor using devm_clk_get_enabled Date: Fri, 26 May 2023 10:36:34 -0400 Message-Id: <20230526143639.1037099-8-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230526143639.1037099-1-Frank.Li@nxp.com> References: <20230526143639.1037099-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0212.namprd13.prod.outlook.com (2603:10b6:a03:2c1::7) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|AS8PR04MB8070:EE_ X-MS-Office365-Filtering-Correlation-Id: 4a2ba342-7aaf-4b99-6a06-08db5df6b429 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { - fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma"); + fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); if (IS_ERR(fsl_edma->dmaclk)) { dev_err(&pdev->dev, "Missing DMA block clock.\n"); return PTR_ERR(fsl_edma->dmaclk); } - - ret = clk_prepare_enable(fsl_edma->dmaclk); - if (ret) { - dev_err(&pdev->dev, "DMA clk block failed.\n"); - return ret; - } } for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { @@ -293,19 +287,12 @@ static int fsl_edma_probe(struct platform_device *pdev) } sprintf(clkname, "dmamux%d", i); - fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname); + fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); if (IS_ERR(fsl_edma->muxclk[i])) { dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); /* on error: disable all previously enabled clks */ - fsl_disable_clocks(fsl_edma, i); return PTR_ERR(fsl_edma->muxclk[i]); } - - ret = clk_prepare_enable(fsl_edma->muxclk[i]); - if (ret) - /* on error: disable all previously enabled clks */ - fsl_disable_clocks(fsl_edma, i); - } fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); @@ -366,7 +353,6 @@ static int fsl_edma_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "Can't register Freescale eDMA engine. (%d)\n", ret); - fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); return ret; } @@ -375,7 +361,6 @@ static int fsl_edma_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma. (%d)\n", ret); dma_async_device_unregister(&fsl_edma->dma_dev); - fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); return ret; }