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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id c25-20020ac24159000000b004cc8196a308sm290902lfi.98.2023.05.30.03.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 03:20:29 -0700 (PDT) From: Konrad Dybcio Date: Tue, 30 May 2023 12:20:19 +0200 Subject: [PATCH 20/20] interconnect: qcom: Divide clk rate by src node bus width MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v1-20-1bf8e6663c4e@linaro.org> References: <20230526-topic-smd_icc-v1-0-1bf8e6663c4e@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v1-0-1bf8e6663c4e@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685442001; l=2453; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=A2xuhtZVawiVfe99Wd1nS5W5Zg3I4zNjmwvGs3s+zi0=; b=hkQXVBfrqCLUDeLOKO2rhZ5dD/3o6xqfIHgI3EXCatqQweKw8yTc3FhFffUDySUhf/LCxUByx +Yb4EPlILCzAbDncb5Lgpb65iONQ74ZFI9cP48gahIkZsk8/cTTuqBk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767315465063223298?= X-GMAIL-MSGID: =?utf-8?q?1767315465063223298?= Ever since the introduction of SMD RPM ICC, we've been dividing the clock rate by the wrong bus width. This has resulted in: - setting wrong (mostly too low) rates, affecting performance - most often /2 or /4 - things like DDR never hit their full potential - the rates were only correct if src bus width == dst bus width for all src, dst pairs on a given bus - Qualcomm using the same wrong logic in their BSP driver in msm-5.x that ships in production devices today - me losing my sanity trying to find this Resolve it by using dst_qn, if it exists. Fixes: 5e4e6c4d3ae0 ("interconnect: qcom: Add QCS404 interconnect provider driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 59be704364bb..58e2a8b1b7c3 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -340,7 +340,7 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider, static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_icc_provider *qp; - struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL; + struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL, *qn = NULL; struct icc_provider *provider; u64 active_rate, sleep_rate; u64 agg_avg[QCOM_SMD_RPM_STATE_NUM], agg_peak[QCOM_SMD_RPM_STATE_NUM]; @@ -353,6 +353,8 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) provider = src->provider; qp = to_qcom_provider(provider); + qn = dst_qn ? dst_qn : src_qn; + qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg); ret = qcom_icc_rpm_set(src_qn, agg_avg); @@ -372,11 +374,11 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) /* Intentionally keep the rates in kHz as that's what RPM accepts */ active_rate = max(agg_avg[QCOM_SMD_RPM_ACTIVE_STATE], agg_peak[QCOM_SMD_RPM_ACTIVE_STATE]); - do_div(active_rate, src_qn->buswidth); + do_div(active_rate, qn->buswidth); sleep_rate = max(agg_avg[QCOM_SMD_RPM_SLEEP_STATE], agg_peak[QCOM_SMD_RPM_SLEEP_STATE]); - do_div(sleep_rate, src_qn->buswidth); + do_div(sleep_rate, qn->buswidth); /* * Downstream checks whether the requested rate is zero, but it makes little sense