From patchwork Mon May 22 12:24:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 97420 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1426552vqo; Mon, 22 May 2023 05:57:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4zzGvRcCzbWnPacrdnP9BCiZV1c3Gn8pTZn58TbSoQPEMbj+nAfYaNOyiHc9/XGlME2Ugh X-Received: by 2002:a05:6a20:3950:b0:100:9969:8cf with SMTP id r16-20020a056a20395000b00100996908cfmr12996931pzg.49.1684760271242; Mon, 22 May 2023 05:57:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684760271; cv=none; d=google.com; s=arc-20160816; b=fhAjZvogfCUvb0Qsgj8T98CDABQ8Tl6AjW/QThe6LcqjRJQGCkpnbaIbJNI5jjvfDJ I1XbpOVrMtHmT5LtuSD95f/8oe19vCUaDViQR6Zo2YPptgiLX7PnqrvPrHBlvJjwihLx mvvD6IaOl6g+HfffVi043BSE4nlkFjHV5wsw/gZOxX4raCMsrP6ZCrCuwD9laEXKx2rl +OyF955X3RkB1dqi6POxJJcO1xlxiGDPrnGSq6Q8XMht64+TzQyUPhEqIbULxc4nQ6cQ dPNFbPDQEBbvifXqe4ctxAmrwEwnhNoEVJIANMJczxtn0+JLxQ7ojmnjTnPatXoCD3QK ngqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=hlxwMsZqvicFQVYA0UDhrWKILTH45Zw6yjCQLnEv22I=; b=bZ2dOZG/g8fj/7LtqFaSriIvoS4o+ub68MnWksGD0mbRgHXF3woY2VYWimspAVGjHm lCvUEwLoXPIlOFcc/oHoubwvjXJT9HVum5vU/LUNvB7fBvgpNHGkBbDvSeKhiksEk7c8 Sp8JzoumH7Q5I7J8ERnfACZnJryjfwVbWvL9hOFhP/mFhdi6B4gFVk1aC5fmLrVrMyjS 0ERVhno+ogNDLnJHgh+XzT22Ve3XjsH8dKUZvlBVMX3NMWg4OSK4yk+KjISuyTmrgvEt vK23uF0Tc3DAEDOnGvMw0VHdOGDrwDWwdVtikqcCbN6aw8qvJrDQvJ0OI4mtQT/Ue0c9 hP6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h189-20020a6383c6000000b00524ea64ba6esi2988555pge.530.2023.05.22.05.57.37; Mon, 22 May 2023 05:57:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234092AbjEVM2E (ORCPT + 99 others); Mon, 22 May 2023 08:28:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233979AbjEVM05 (ORCPT ); Mon, 22 May 2023 08:26:57 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 46F8310DB; Mon, 22 May 2023 05:25:09 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A6EB71576; Mon, 22 May 2023 05:25:44 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 062FA3F59C; Mon, 22 May 2023 05:24:57 -0700 (PDT) From: Mark Rutland To: linux-kernel@vger.kernel.org Cc: akiyks@gmail.com, boqun.feng@gmail.com, corbet@lwn.net, keescook@chromium.org, linux-arch@vger.kernel.org, linux@armlinux.org.uk, linux-doc@vger.kernel.org, mark.rutland@arm.com, paulmck@kernel.org, peterz@infradead.org, sstabellini@kernel.org, will@kernel.org Subject: [PATCH 09/26] locking/atomic: parisc: add preprocessor symbols Date: Mon, 22 May 2023 13:24:12 +0100 Message-Id: <20230522122429.1915021-10-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230522122429.1915021-1-mark.rutland@arm.com> References: <20230522122429.1915021-1-mark.rutland@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766599186280862480?= X-GMAIL-MSGID: =?utf-8?q?1766599186280862480?= Some atomics can be implemented in several different ways, e.g. FULL/ACQUIRE/RELEASE ordered atomics can be implemented in terms of RELAXED atomics, and ACQUIRE/RELEASE/RELAXED can be implemented in terms of FULL ordered atomics. Other atomics are optional, and don't exist in some configurations (e.g. not all architectures implement the 128-bit cmpxchg ops). Subsequent patches will require that architectures define a preprocessor symbol for any atomic (or ordering variant) which is optional. This will make the fallback ifdeffery more robust, and simplify future changes. Add the required definitions to arch/parisc. Signed-off-by: Mark Rutland Cc: Boqun Feng Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Will Deacon --- arch/parisc/include/asm/atomic.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h index 0b3f64c92e3c0..d4f023887ff87 100644 --- a/arch/parisc/include/asm/atomic.h +++ b/arch/parisc/include/asm/atomic.h @@ -118,6 +118,11 @@ static __inline__ int arch_atomic_fetch_##op(int i, atomic_t *v) \ ATOMIC_OPS(add, +=) ATOMIC_OPS(sub, -=) +#define arch_atomic_add_return arch_atomic_add_return +#define arch_atomic_sub_return arch_atomic_sub_return +#define arch_atomic_fetch_add arch_atomic_fetch_add +#define arch_atomic_fetch_sub arch_atomic_fetch_sub + #undef ATOMIC_OPS #define ATOMIC_OPS(op, c_op) \ ATOMIC_OP(op, c_op) \ @@ -127,6 +132,10 @@ ATOMIC_OPS(and, &=) ATOMIC_OPS(or, |=) ATOMIC_OPS(xor, ^=) +#define arch_atomic_fetch_and arch_atomic_fetch_and +#define arch_atomic_fetch_or arch_atomic_fetch_or +#define arch_atomic_fetch_xor arch_atomic_fetch_xor + #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN @@ -181,6 +190,11 @@ static __inline__ s64 arch_atomic64_fetch_##op(s64 i, atomic64_t *v) \ ATOMIC64_OPS(add, +=) ATOMIC64_OPS(sub, -=) +#define arch_atomic64_add_return arch_atomic64_add_return +#define arch_atomic64_sub_return arch_atomic64_sub_return +#define arch_atomic64_fetch_add arch_atomic64_fetch_add +#define arch_atomic64_fetch_sub arch_atomic64_fetch_sub + #undef ATOMIC64_OPS #define ATOMIC64_OPS(op, c_op) \ ATOMIC64_OP(op, c_op) \ @@ -190,6 +204,10 @@ ATOMIC64_OPS(and, &=) ATOMIC64_OPS(or, |=) ATOMIC64_OPS(xor, ^=) +#define arch_atomic64_fetch_and arch_atomic64_fetch_and +#define arch_atomic64_fetch_or arch_atomic64_fetch_or +#define arch_atomic64_fetch_xor arch_atomic64_fetch_xor + #undef ATOMIC64_OPS #undef ATOMIC64_FETCH_OP #undef ATOMIC64_OP_RETURN