Message ID | 20230522093002.75137-2-angelogioacchino.delregno@collabora.com |
---|---|
State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h14-20020a17090a604e00b00252fc82b3afsi4394012pjm.128.2023.05.22.02.54.04; Mon, 22 May 2023 02:54:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=AcDyWd4R; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232195AbjEVJaS (ORCPT <rfc822;cscallsign@gmail.com> + 99 others); Mon, 22 May 2023 05:30:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231409AbjEVJaN (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Mon, 22 May 2023 05:30:13 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 581779D; Mon, 22 May 2023 02:30:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:a962:cd4d:a84:1eab]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E658166058F2; Mon, 22 May 2023 10:30:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1684747809; bh=8THYe79i65UdHa2AS5CAUyFodTMPPnYlaLqy/e9sDbY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AcDyWd4R9EBwLOnEZezjmVfSgRSLA2+plkuc7SNL0Bwl1urZ2d/QO4tAiqHYNfkLk iWuIB8mOVV7oO7hL0X66aiRBP97hM9uJSmjGQCFnewMqIS2+M2ACKrhWfqihUvnEkB 6wH5W1HglBuqxomb3ajCfrNo4HwQ5H5sQVX65uudy0qXV2J8vTAeu3M+sisYN3+Um8 DEDrv28AVCs14mRDrMU8iopM7v6618t+wMYUjytO9D/f1n+5NwxhtP8PRb2Qwm5pDB MpkAWXhzbM/RDLyRRppMqfhGoTkKD1NFX3IUYL4fLhfD5J/dJu7eY6dpTZet5dxnQG thtJRIMst2x0g== From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, weiyi.lu@mediatek.com, ikjn@chromium.org, chun-jie.chen@mediatek.com, tinghan.shen@mediatek.com, seiya.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Subject: [PATCH 1/2] arm64: dts: mediatek: mt8192: Make sure MSDCPLL's rate is 400MHz Date: Mon, 22 May 2023 11:30:01 +0200 Message-Id: <20230522093002.75137-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230522093002.75137-1-angelogioacchino.delregno@collabora.com> References: <20230522093002.75137-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766587636307648518?= X-GMAIL-MSGID: =?utf-8?q?1766587636307648518?= |
Series |
MT8192/95: Set correct MSDCPLL rate
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Commit Message
AngeloGioacchino Del Regno
May 22, 2023, 9:30 a.m. UTC
Some bootloaders will set MSDCPLL's rate lower than 400MHz: what I have
seen is this clock being set at around 384MHz.
This is a performance concern (and possibly a stability one, for picky
eMMC/SD cards) as the MSDC controller's internal divier will choose a
frequency that is lower than expected, in the end causing a difference
in the expected mmc/sd device's timings.
Make sure that the MSDCPLL frequency is always set to 400MHz to both
improve performance and reliability of the sd/mmc storage.
Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
1 file changed, 2 insertions(+)
Comments
Hi AngeloGioacchino, On Mon, 2023-05-22 at 11:30 +0200, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > Some bootloaders will set MSDCPLL's rate lower than 400MHz: what I have > seen is this clock being set at around 384MHz. > This is a performance concern (and possibly a stability one, for picky > eMMC/SD cards) as the MSDC controller's internal divier will choose a > frequency that is lower than expected, in the end causing a difference > in the expected mmc/sd device's timings. > > Make sure that the MSDCPLL frequency is always set to 400MHz to both > improve performance and reliability of the sd/mmc storage. > > Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 5c30caf74026..6fc14004f6fd 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -677,6 +677,8 @@ apmixedsys: syscon@1000c000 { > compatible = "mediatek,mt8192-apmixedsys", "syscon"; > reg = <0 0x1000c000 0 0x1000>; > #clock-cells = <1>; > + assigned-clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; > + assigned-clock-rates = <400000000>; > }; > > systimer: timer@10017000 { > -- > 2.40.1 > Comment from mtk emmc owner, "As we all know, the clock has some jitter, when we set MSDCPLL to 400M, but the actual measurement is not exactly 200M. For eMMC, the spec stipulates that clock cannot exceed 200M. If MSDCPLL is set to 400M, the actual measurement may exceed the spec. So we set MSDCPLL to 384M in the bootloader stage to avoid exceeding the spec." -- Best regards, TingHan
On 15/06/2023 11:51, TingHan Shen (沈廷翰) wrote: > Hi AngeloGioacchino, > > On Mon, 2023-05-22 at 11:30 +0200, AngeloGioacchino Del Regno wrote: >> External email : Please do not click links or open attachments until you have verified the sender or the content. >> >> >> Some bootloaders will set MSDCPLL's rate lower than 400MHz: what I have >> seen is this clock being set at around 384MHz. >> This is a performance concern (and possibly a stability one, for picky >> eMMC/SD cards) as the MSDC controller's internal divier will choose a >> frequency that is lower than expected, in the end causing a difference >> in the expected mmc/sd device's timings. >> >> Make sure that the MSDCPLL frequency is always set to 400MHz to both >> improve performance and reliability of the sd/mmc storage. >> >> Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >> index 5c30caf74026..6fc14004f6fd 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >> @@ -677,6 +677,8 @@ apmixedsys: syscon@1000c000 { >> compatible = "mediatek,mt8192-apmixedsys", "syscon"; >> reg = <0 0x1000c000 0 0x1000>; >> #clock-cells = <1>; >> + assigned-clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; >> + assigned-clock-rates = <400000000>; >> }; >> >> systimer: timer@10017000 { >> -- >> 2.40.1 >> > > Comment from mtk emmc owner, > > "As we all know, the clock has some jitter, when we set MSDCPLL to 400M, > but the actual measurement is not exactly 200M. > For eMMC, the spec stipulates that clock cannot exceed 200M. > If MSDCPLL is set to 400M, the actual measurement may exceed the spec. > So we set MSDCPLL to 384M in the bootloader stage to avoid exceeding the spec." > Thanks for the feedback. Given that I'm not aware of any regressions that got fixed by this commits I will drop this series for now. We can keep on the discussion and if needed add them in a later stage. Regards, Matthias
Il 15/06/23 13:16, Matthias Brugger ha scritto: > > > On 15/06/2023 11:51, TingHan Shen (沈廷翰) wrote: >> Hi AngeloGioacchino, >> >> On Mon, 2023-05-22 at 11:30 +0200, AngeloGioacchino Del Regno wrote: >>> External email : Please do not click links or open attachments until you have >>> verified the sender or the content. >>> >>> >>> Some bootloaders will set MSDCPLL's rate lower than 400MHz: what I have >>> seen is this clock being set at around 384MHz. >>> This is a performance concern (and possibly a stability one, for picky >>> eMMC/SD cards) as the MSDC controller's internal divier will choose a >>> frequency that is lower than expected, in the end causing a difference >>> in the expected mmc/sd device's timings. >>> >>> Make sure that the MSDCPLL frequency is always set to 400MHz to both >>> improve performance and reliability of the sd/mmc storage. >>> >>> Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") >>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >>> --- >>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> index 5c30caf74026..6fc14004f6fd 100644 >>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> @@ -677,6 +677,8 @@ apmixedsys: syscon@1000c000 { >>> compatible = "mediatek,mt8192-apmixedsys", "syscon"; >>> reg = <0 0x1000c000 0 0x1000>; >>> #clock-cells = <1>; >>> + assigned-clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; >>> + assigned-clock-rates = <400000000>; >>> }; >>> >>> systimer: timer@10017000 { >>> -- >>> 2.40.1 >>> >> >> Comment from mtk emmc owner, >> >> "As we all know, the clock has some jitter, when we set MSDCPLL to 400M, >> but the actual measurement is not exactly 200M. >> For eMMC, the spec stipulates that clock cannot exceed 200M. >> If MSDCPLL is set to 400M, the actual measurement may exceed the spec. >> So we set MSDCPLL to 384M in the bootloader stage to avoid exceeding the spec." >> Thanks for the comment, I haven't seen any issue with this commit, if not a slight performance improvement, on MT8192 and MT8195, but if there's risk to overclock the card, then it's not ok. In any case, what is the expected jitter percentage? eMMC/SD cards do expect jitter by spec anyway. Thanks, Angelo > > Thanks for the feedback. Given that I'm not aware of any regressions that got fixed > by this commits I will drop this series for now. We can keep on the discussion and > if needed add them in a later stage. > > Regards, > Matthias >
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 5c30caf74026..6fc14004f6fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -677,6 +677,8 @@ apmixedsys: syscon@1000c000 { compatible = "mediatek,mt8192-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; #clock-cells = <1>; + assigned-clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; + assigned-clock-rates = <400000000>; }; systimer: timer@10017000 {