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E.g the default ioremap_uc() returning NULL. We also massaged various headers to avoid nested includes. Signed-off-by: Baoquan He Signed-off-by: Jiaxun Yang [jiaxun.yang@flygoat.com: Massage more headers, fix ioport defines] Cc: Thomas Bogendoerfer Cc: Huacai Chen Cc: Jiaxun Yang Cc: linux-mips@vger.kernel.org --- Tested against qemu malta 34Kf, boston I6500, Loongson64, hopefully everything is fine now. --- arch/mips/include/asm/io.h | 65 +++++++++++++++++++++++++++++---- arch/mips/include/asm/mmiowb.h | 4 +- arch/mips/include/asm/smp-ops.h | 2 - arch/mips/include/asm/smp.h | 4 +- arch/mips/kernel/setup.c | 1 + arch/mips/pci/pci-ip27.c | 3 ++ 6 files changed, 64 insertions(+), 15 deletions(-) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index cc28d207a061..8508d01fb75e 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -15,7 +15,6 @@ #define ARCH_HAS_IOREMAP_WC #include -#include #include #include @@ -28,7 +27,6 @@ #include #include #include -#include #include #include @@ -44,6 +42,11 @@ # define __raw_ioswabq(a, x) (x) # define ____raw_ioswabq(a, x) (x) +# define _ioswabb ioswabb +# define _ioswabw ioswabw +# define _ioswabl ioswabl +# define _ioswabq ioswabq + # define __relaxed_ioswabb ioswabb # define __relaxed_ioswabw ioswabw # define __relaxed_ioswabl ioswabl @@ -129,6 +132,7 @@ static inline phys_addr_t virt_to_phys(const volatile void *x) * almost all conceivable cases a device driver should not be using * this function */ +#define phys_to_virt phys_to_virt static inline void * phys_to_virt(unsigned long address) { return __va(address); @@ -297,9 +301,9 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ return pfx##ioswab##bwlq(__mem, __val); \ } -#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \ +#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax) \ \ -static inline void pfx##out##bwlq##p(type val, unsigned long port) \ +static inline void pfx##out##bwlq(type val, unsigned long port) \ { \ volatile type *__addr; \ type __val; \ @@ -319,7 +323,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ *__addr = __val; \ } \ \ -static inline type pfx##in##bwlq##p(unsigned long port) \ +static inline type pfx##in##bwlq(unsigned long port) \ { \ volatile type *__addr; \ type __val; \ @@ -361,11 +365,10 @@ __BUILD_MEMORY_PFX(__mem_, q, u64, 0) #endif #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ - __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \ - __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p) + __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0) #define BUILDIO_IOPORT(bwlq, type) \ - __BUILD_IOPORT_PFX(, bwlq, type) \ + __BUILD_IOPORT_PFX(_, bwlq, type) \ __BUILD_IOPORT_PFX(__mem_, bwlq, type) BUILDIO_IOPORT(b, u8) @@ -481,14 +484,17 @@ BUILDSTRING(l, u32) BUILDSTRING(q, u64) #endif +#define memset_io memset_io static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) { memset((void __force *) addr, val, count); } +#define memcpy_fromio memcpy_fromio static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) { memcpy(dst, (void __force *) src, count); } +#define memcpy_toio memcpy_toio static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) { memcpy((void __force *) dst, src, count); @@ -549,6 +555,47 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) + +#define __raw_readb __raw_readb +#define __raw_readw __raw_readw +#define __raw_readl __raw_readl +#define __raw_readq __raw_readq +#define __raw_writeb __raw_writeb +#define __raw_writew __raw_writew +#define __raw_writel __raw_writel +#define __raw_writeq __raw_writeq + +#define readb readb +#define readw readw +#define readl readl +#define writeb writeb +#define writew writew +#define writel writel + +#define readsb readsb +#define readsw readsw +#define readsl readsl +#define readsq readsq +#define writesb writesb +#define writesw writesw +#define writesl writesl +#define writesq writesq + +#define _inb _inb +#define _inw _inw +#define _inl _inl +#define insb insb +#define insw insw +#define insl insl + +#define _outb _outb +#define _outw _outw +#define _outl _outl +#define outsb outsb +#define outsw outsw +#define outsl outsl + + /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem * access @@ -557,4 +604,6 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); void __ioread64_copy(void *to, const void __iomem *from, size_t count); +#include + #endif /* _ASM_IO_H */ diff --git a/arch/mips/include/asm/mmiowb.h b/arch/mips/include/asm/mmiowb.h index a40824e3ef8e..cf27752fd220 100644 --- a/arch/mips/include/asm/mmiowb.h +++ b/arch/mips/include/asm/mmiowb.h @@ -2,9 +2,9 @@ #ifndef _ASM_MMIOWB_H #define _ASM_MMIOWB_H -#include +#include -#define mmiowb() iobarrier_w() +#define mmiowb() wmb() #include diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index 5719ff49eff1..a6941b7f0cc0 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -13,8 +13,6 @@ #include -#include - #ifdef CONFIG_SMP #include diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index aab8981bc32c..125c3494a010 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -11,13 +11,11 @@ #ifndef __ASM_SMP_H #define __ASM_SMP_H -#include +#include #include -#include #include #include -#include #include extern int smp_num_siblings; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index febdc5564638..f9f149928e46 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index d85cbf84e41c..973faea61cad 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -7,6 +7,9 @@ * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ + +#include + #include #include #include