diff mbox series

[V2,1/2] dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 bindings

Message ID 20230519085723.15601-2-quic_devipriy@quicinc.com
State New
Headers
Series Add support for PCIe PHY in IPQ9574 |

Commit Message

Devi Priya May 19, 2023, 8:57 a.m. UTC 
  Add bindings for the PCIe QMP PHYs found on IPQ9574.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 Changes in V2:
	- Picked up the R-b tag
	- Did not convert the clock IDs to numerical values as the clock
	  header (dependent patch) is merged in latest rc1.

 .../phy/qcom,ipq9574-qmp-pcie-phy.yaml        | 90 +++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml

Comments

Rob Herring May 19, 2023, 9:23 a.m. UTC | #1 
On Fri, 19 May 2023 14:27:22 +0530, Devi Priya wrote:
> Add bindings for the PCIe QMP PHYs found on IPQ9574.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>  Changes in V2:
> 	- Picked up the R-b tag
> 	- Did not convert the clock IDs to numerical values as the clock
> 	  header (dependent patch) is merged in latest rc1.
> 
>  .../phy/qcom,ipq9574-qmp-pcie-phy.yaml        | 90 +++++++++++++++++++
>  1 file changed, 90 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.example.dts:29.26-27 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1512: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230519085723.15601-2-quic_devipriy@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
Devi Priya May 19, 2023, 9:32 a.m. UTC | #2 
On 5/19/2023 2:53 PM, Rob Herring wrote:
> 
> On Fri, 19 May 2023 14:27:22 +0530, Devi Priya wrote:
>> Add bindings for the PCIe QMP PHYs found on IPQ9574.
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>>   Changes in V2:
>> 	- Picked up the R-b tag
>> 	- Did not convert the clock IDs to numerical values as the clock
>> 	  header (dependent patch) is merged in latest rc1.
>>
>>   .../phy/qcom,ipq9574-qmp-pcie-phy.yaml        | 90 +++++++++++++++++++
>>   1 file changed, 90 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
>>
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> Error: Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.example.dts:29.26-27 syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.example.dtb] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [Makefile:1512: dt_binding_check] Error 2
> 
Sorry, The PCIe clocks are added part of the below series:
https://lore.kernel.org/linux-arm-msm/20230519090219.15925-1-quic_devipriy@quicinc.com/

Thanks,
Devi Priya
> doc reference errors (make refcheckdocs):
> 
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230519085723.15601-2-quic_devipriy@quicinc.com
> 
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
>
Dmitry Baryshkov May 21, 2023, 8:57 p.m. UTC | #3 
On 19/05/2023 11:57, Devi Priya wrote:
> Add bindings for the PCIe QMP PHYs found on IPQ9574.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>   Changes in V2:
> 	- Picked up the R-b tag
> 	- Did not convert the clock IDs to numerical values as the clock
> 	  header (dependent patch) is merged in latest rc1.
> 
>   .../phy/qcom,ipq9574-qmp-pcie-phy.yaml        | 90 +++++++++++++++++++
>   1 file changed, 90 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
> new file mode 100644
> index 000000000000..7c8012647051
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,ipq9574-qmp-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QMP PHY controller (PCIe, IPQ9574)
> +
> +maintainers:
> +  - Vinod Koul <vkoul@kernel.org>
> +
> +description:
> +  The QMP PHY controller supports physical layer functionality for a number of
> +  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,ipq9574-qmp-gen3x1-pcie-phy
> +      - qcom,ipq9574-qmp-gen3x2-pcie-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 5
> +
> +  clock-names:
> +    items:
> +      - const: aux
> +      - const: cfg_ahb
> +      - const: anoc_lane
> +      - const: snoc_lane
> +      - const: pipe

Could you please reorder the clocks in the following way:
- aux
- cfg_ahb
- pipe
- .. the rest

This will allow us to use this schema for other IPQ QMP PCIe PHYs.

> +
> +  resets:
> +    maxItems: 2
> +
> +  reset-names:
> +    items:
> +      - const: phy
> +      - const: common
> +
> +  "#clock-cells":
> +    const: 0
> +
> +  clock-output-names:
> +    maxItems: 1
> +
> +  "#phy-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - "#clock-cells"
> +  - clock-output-names
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +    #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +
> +    pcie0_phy: phy@84000 {
> +      compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> +      reg = <0x00084000 0x1000>;
> +
> +      clocks = <&gcc GCC_PCIE0_AUX_CLK>,
> +               <&gcc GCC_PCIE0_AHB_CLK>,
> +               <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
> +               <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>,
> +               <&gcc GCC_PCIE0_PIPE_CLK>;
> +      clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane", "pipe";
> +
> +      resets = <&gcc GCC_PCIE0_PHY_BCR>,
> +               <&gcc GCC_PCIE0PHY_PHY_BCR>;
> +      reset-names = "phy", "common";
> +
> +      #clock-cells = <0>;
> +      clock-output-names = "gcc_pcie0_pipe_clk_src";
> +
> +      #phy-cells = <0>;
> +    };
Devi Priya May 24, 2023, 5:49 a.m. UTC | #4 
On 5/22/2023 2:27 AM, Dmitry Baryshkov wrote:
> On 19/05/2023 11:57, Devi Priya wrote:
>> Add bindings for the PCIe QMP PHYs found on IPQ9574.
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>>   Changes in V2:
>>     - Picked up the R-b tag
>>     - Did not convert the clock IDs to numerical values as the clock
>>       header (dependent patch) is merged in latest rc1.
>>
>>   .../phy/qcom,ipq9574-qmp-pcie-phy.yaml        | 90 +++++++++++++++++++
>>   1 file changed, 90 insertions(+)
>>   create mode 100644 
>> Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
>>
>> diff --git 
>> a/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml 
>> b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
>> new file mode 100644
>> index 000000000000..7c8012647051
>> --- /dev/null
>> +++ 
>> b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
>> @@ -0,0 +1,90 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/qcom,ipq9574-qmp-pcie-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QMP PHY controller (PCIe, IPQ9574)
>> +
>> +maintainers:
>> +  - Vinod Koul <vkoul@kernel.org>
>> +
>> +description:
>> +  The QMP PHY controller supports physical layer functionality for a 
>> number of
>> +  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - qcom,ipq9574-qmp-gen3x1-pcie-phy
>> +      - qcom,ipq9574-qmp-gen3x2-pcie-phy
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    maxItems: 5
>> +
>> +  clock-names:
>> +    items:
>> +      - const: aux
>> +      - const: cfg_ahb
>> +      - const: anoc_lane
>> +      - const: snoc_lane
>> +      - const: pipe
> 
> Could you please reorder the clocks in the following way:
> - aux
> - cfg_ahb
> - pipe
> - .. the rest
> 
> This will allow us to use this schema for other IPQ QMP PCIe PHYs.
Sure, will update.

Thanks,
Devi Priya
> 
>> +
>> +  resets:
>> +    maxItems: 2
>> +
>> +  reset-names:
>> +    items:
>> +      - const: phy
>> +      - const: common
>> +
>> +  "#clock-cells":
>> +    const: 0
>> +
>> +  clock-output-names:
>> +    maxItems: 1
>> +
>> +  "#phy-cells":
>> +    const: 0
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - clock-names
>> +  - resets
>> +  - reset-names
>> +  - "#clock-cells"
>> +  - clock-output-names
>> +  - "#phy-cells"
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> +    #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> +
>> +    pcie0_phy: phy@84000 {
>> +      compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> +      reg = <0x00084000 0x1000>;
>> +
>> +      clocks = <&gcc GCC_PCIE0_AUX_CLK>,
>> +               <&gcc GCC_PCIE0_AHB_CLK>,
>> +               <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
>> +               <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>,
>> +               <&gcc GCC_PCIE0_PIPE_CLK>;
>> +      clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane", "pipe";
>> +
>> +      resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> +               <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> +      reset-names = "phy", "common";
>> +
>> +      #clock-cells = <0>;
>> +      clock-output-names = "gcc_pcie0_pipe_clk_src";
>> +
>> +      #phy-cells = <0>;
>> +    };
>
Krzysztof Kozlowski May 30, 2023, 12:56 p.m. UTC | #5 
On Fri, 19 May 2023 14:27:22 +0530, Devi Priya wrote:
> Add bindings for the PCIe QMP PHYs found on IPQ9574.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>  Changes in V2:
> 	- Picked up the R-b tag
> 	- Did not convert the clock IDs to numerical values as the clock
> 	  header (dependent patch) is merged in latest rc1.
> 
>  .../phy/qcom,ipq9574-qmp-pcie-phy.yaml        | 90 +++++++++++++++++++
>  1 file changed, 90 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.example.dts:29.26-27 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1512: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1783652

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
new file mode 100644
index 000000000000..7c8012647051
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml
@@ -0,0 +1,90 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,ipq9574-qmp-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP PHY controller (PCIe, IPQ9574)
+
+maintainers:
+  - Vinod Koul <vkoul@kernel.org>
+
+description:
+  The QMP PHY controller supports physical layer functionality for a number of
+  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+  compatible:
+    enum:
+      - qcom,ipq9574-qmp-gen3x1-pcie-phy
+      - qcom,ipq9574-qmp-gen3x2-pcie-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 5
+
+  clock-names:
+    items:
+      - const: aux
+      - const: cfg_ahb
+      - const: anoc_lane
+      - const: snoc_lane
+      - const: pipe
+
+  resets:
+    maxItems: 2
+
+  reset-names:
+    items:
+      - const: phy
+      - const: common
+
+  "#clock-cells":
+    const: 0
+
+  clock-output-names:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - "#clock-cells"
+  - clock-output-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+    #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+
+    pcie0_phy: phy@84000 {
+      compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+      reg = <0x00084000 0x1000>;
+
+      clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+               <&gcc GCC_PCIE0_AHB_CLK>,
+               <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
+               <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>,
+               <&gcc GCC_PCIE0_PIPE_CLK>;
+      clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane", "pipe";
+
+      resets = <&gcc GCC_PCIE0_PHY_BCR>,
+               <&gcc GCC_PCIE0PHY_PHY_BCR>;
+      reset-names = "phy", "common";
+
+      #clock-cells = <0>;
+      clock-output-names = "gcc_pcie0_pipe_clk_src";
+
+      #phy-cells = <0>;
+    };