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Thu, 18 May 2023 19:56:06 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 4/5] iommu/amd: Do not Invalidate IRT when disable IRTE caching Date: Thu, 18 May 2023 20:55:28 -0400 Message-ID: <20230519005529.28171-5-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> References: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT063:EE_|DM6PR12MB4123:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e2a9398-dd71-4a64-32f1-08db5803d4f2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rLVYZFY0uUUPN++PsohbtXEg5Hb6N5zfhou3gn5ntPxQYv3aIo9i88yZQIlIJzBvNmPJdMXZc9r5JSEGjGHmzZKoOtwvtaVwRvuNkUp2KImEq04cd6eeYsNgxjzX5BcG6lxB+KIPjXJ03Top90AwncOexZ1OUN7uj0GyzLfGFHZdj2+tjFhp1U/FRhawdTjzIh7+sxbabDFHfhMWtOsa7TAeyCDdDbellvkCXYlOINrVPGaAM26rg8aa0FBYsKKiqQaGoHcYf1tQz8I2jU1zCF4VC4x0bc2wZV71vpXr+E1ni/jPalGVoJ0T4TMihUTXB638KnyY9AnKM7obxiukJFCa+guHKvNSBPtzNAEH2OdW8fqAhZ6fNCqd/xKpHy61N1mjGeZWo2CweQc/1RkqpVRKlrjCEgID2K6VwloqsaaCGrVneDIIluy0SHWXR0t+Bm3+0/MMk2Pje2TUNFESQDNSm6qEMJ6lLYKCiPa9CJWAwBH89LP1BOxtPirIHVgWXmfXkiGq2sd1M0E7suAXZaV46UJISvV1PRXR2JrGbvYk8yu9sah8QJZVjIym0G+CZS9PRMP3Gy0xghEUgSmk/5fL0hiiSndphSLW5JJu4+KPvFslBwGVf/upOAjf30dUlMRnFgd6MQCH7jMlu9TbqaYYPmpMMGvy0mp7PDOouIjaQ6w/nXrMo57OUX17Uz57IfFcY+PAlGprA2qUfAm0I/QYfCTHretFnEnsHzyF6QXRWR9m0StBFdt0bJ911bcN7Uu9o0n/hM+JXOkXVjPBrg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(39860400002)(376002)(136003)(451199021)(36840700001)(40470700004)(46966006)(1076003)(26005)(7696005)(40460700003)(36860700001)(36756003)(2616005)(40480700001)(47076005)(83380400001)(426003)(336012)(86362001)(82310400005)(82740400003)(356005)(16526019)(186003)(81166007)(110136005)(316002)(54906003)(44832011)(478600001)(2906002)(4326008)(8936002)(8676002)(41300700001)(5660300002)(70586007)(70206006)(6666004)(36900700001);DIR:OUT;SFP:1101; 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Therefore, add logic to bypass the operation. Suggested-by: Joao Martins Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jerry Snitselaar --- drivers/iommu/amd/iommu.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 0c4a2796bb0a..51c2b018433d 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1273,12 +1273,24 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) u32 devid; u16 last_bdf = iommu->pci_seg->last_bdf; + if (iommu->irtcachedis_enabled) + return; + for (devid = 0; devid <= last_bdf; devid++) iommu_flush_irt(iommu, devid); iommu_completion_wait(iommu); } +static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid) +{ + if (iommu->irtcachedis_enabled) + return; + + iommu_flush_irt(iommu, devid); + iommu_completion_wait(iommu); +} + void iommu_flush_all_caches(struct amd_iommu *iommu) { if (iommu_feature(iommu, FEATURE_IA)) { @@ -3028,8 +3040,7 @@ static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); return 0; } @@ -3048,8 +3059,7 @@ static int modify_irte(struct amd_iommu *iommu, table->table[index] = irte->val; raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); return 0; } @@ -3067,8 +3077,7 @@ static void free_irte(struct amd_iommu *iommu, u16 devid, int index) iommu->irte_ops->clear_allocated(table, index); raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); } static void irte_prepare(void *entry,