From patchwork Thu May 18 10:48:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 95774 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp400226vqo; Thu, 18 May 2023 04:00:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4mA4X1izMveDg2g0/cr285qfUch7UDWuGuPZAHOyQfgoqw+MhtvtQ2xRDt1HOh8YdykInk X-Received: by 2002:a05:6a00:80d:b0:63d:5de3:b3f2 with SMTP id m13-20020a056a00080d00b0063d5de3b3f2mr4160610pfk.18.1684407656817; Thu, 18 May 2023 04:00:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684407656; cv=none; d=google.com; s=arc-20160816; b=LX/HXJLgbUGAN5G4K22wm/jTFTQFeo/4/XHVQUAmFrkAPkn1KWVdaZWo73SEu9bj0Y 5w+XtM+lqJRotzpaAUx+tPmVgblpiXg2C+XW6o70DBh1sjmzuUuW57Y32rGY66/B7Opn pCdjtsQw2sVgS6Sk2U+BweowfG1TZUbQ+TA6aZ+Ka91A8kykbFU/ypp+qZ3d3JU+3/dR 9EY8FaM+c4pqO2TzXRT7EC7p4yhYJFbsubpBbzu0Xa78VB0HKg1B5Aq8dnNnukzZmy9a /NRkesbaT9L4zBQoirDyrxoYYLWhRBS/VVE0SQx/53BF/DJXTQrKIQc4Zorn5LWrAnXO 0tfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Be7m4bRvQfs02FzGdIg8G5tviMUBM3/phQe1MxIXOoc=; b=j0d0sUEHruxL42mL8m1i5Gpc12BPB7Qvz2cclULa89c6wAeohY4/48QC5CfwogQ3JX 9SVGAcqViefCy+Vn7r1ISyUf+FmBi02dJzVd0HNkuIiE4vr2Ee35s1hVrSRN46x6345Q 6Sj6SGGLQuHQrKI3R2LoLAuulVA4nn2hwk6PzPbnCuZyNq4PqwSSZFPDw+EwGevmlA33 o08V9X98DP9LY6vvqLl3sp+0qKUxUi/ms3iZJBg+1bnIqRUZhbgijEhhi8StOlj9aTJH d6unWB4qOzeH8WgpWjNfaxtWB8x47PD+jc/545+q/WUTbGNT/XAYUo2+zrC1lrkUtDYh GVeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=EZWGYPGc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x16-20020aa79a50000000b006438e35303csi882026pfj.260.2023.05.18.04.00.40; Thu, 18 May 2023 04:00:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=EZWGYPGc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230467AbjERKtm (ORCPT + 99 others); Thu, 18 May 2023 06:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbjERKtM (ORCPT ); Thu, 18 May 2023 06:49:12 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78CB010C9 for ; Thu, 18 May 2023 03:49:10 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:a962:cd4d:a84:1eab]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8A4A766059A5; Thu, 18 May 2023 11:49:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1684406949; bh=JAQLLPMkc+mUKKZA9j94i5lIpT3amMIqAM03uzJuyWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EZWGYPGcuCfa6Oi0kTjcUfvBGSpQmtvBXWH9E/h8WZu1klqbaAaYPln7meT6uh46F +3FG8tlpxeE1N6dvFHIoKDuyfJxHHli9Ale26Covbt/pqAvVUZ/dffDCzvjwj/JJf3 99rrJ2DbHdz1RQ3v9AnA6QsAX20gU3oohqp17HYZjFs8WXJlTh2GVALcUCPIukd+Lm NNNzHYCA9hGndCJVoGbPceiT04b+FJX2J0btJMSxrBYGBWc0hzpjgrRSQsK4Denfip SOZ4nPsQ+JK1bItPL2Il0oRt7+rWIuBkghVlpTq3Tf2I5C+wMIGIP+6DxtI4CKwFqm g91/AP5X0Bljg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v4 08/11] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Thu, 18 May 2023 12:48:54 +0200 Message-Id: <20230518104857.124265-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230518104857.124265-1-angelogioacchino.delregno@collabora.com> References: <20230518104857.124265-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766229442778521784?= X-GMAIL-MSGID: =?utf-8?q?1766229442778521784?= Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 78 +++++++++++++++-------- 1 file changed, 51 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 62e1e50d2671..a05c445367ee 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -25,6 +25,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -38,6 +40,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; u8 lut_bits; }; @@ -84,9 +87,10 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; - u16 lut_size; + u16 lut_bank_size, lut_size; u8 lut_bits; - u32 cfg_val, word; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -94,43 +98,61 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; + lut_bank_size = gamma->data->lut_bank_size; lut_bits = gamma->data->lut_bits; lut_size = gamma->data->lut_size; } else { lut_diff = false; + lut_bank_size = LUT_SIZE_DEFAULT; lut_bits = LUT_BITS_DEFAULT; lut_size = LUT_SIZE_DEFAULT; } + if (lut_bank_size) + num_lut_banks = lut_size / lut_bank_size; + else + num_lut_banks = 1; + cfg_val = readl(regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red = drm_color_lut_extract(lut[i].red, lut_bits); - hwlut.green = drm_color_lut_extract(lut[i].green, lut_bits); - hwlut.blue = drm_color_lut_extract(lut[i].blue, lut_bits); - - if (!lut_diff || (i % 2 == 0)) { - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, lut_bits); - - diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, lut_bits); - - diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, lut_bits); - - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + + for (cur_bank = 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val = FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, regs + DISP_GAMMA_BANK); + } + + for (i = 0; i < lut_bank_size; i++) { + int n = (cur_bank * lut_bank_size) + i; + struct drm_color_lut diff, hwlut; + + hwlut.red = drm_color_lut_extract(lut[n].red, lut_bits); + hwlut.green = drm_color_lut_extract(lut[n].green, lut_bits); + hwlut.blue = drm_color_lut_extract(lut[n].blue, lut_bits); + + if (!lut_diff || (i % 2 == 0)) { + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red = lut[n].red - lut[n - 1].red; + diff.red = drm_color_lut_extract(diff.red, lut_bits); + + diff.green = lut[n].green - lut[n - 1].green; + diff.green = drm_color_lut_extract(diff.green, lut_bits); + + diff.blue = lut[n].blue - lut[n - 1].blue; + diff.blue = drm_color_lut_extract(diff.blue, lut_bits); + + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } /* Enable the gamma table */ @@ -241,11 +263,13 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_bank_size = 512, .lut_bits = 10, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { + .lut_bank_size = 512, .lut_bits = 10, .lut_diff = true, .lut_size = 512,