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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m9-20020a170902db0900b001ac68acb1e8si21820664plx.518.2023.05.16.21.36.37; Tue, 16 May 2023 21:36:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=rg5FCpR+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230127AbjEQEfr (ORCPT + 99 others); Wed, 17 May 2023 00:35:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231667AbjEQEfp (ORCPT ); Wed, 17 May 2023 00:35:45 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36EFA2D4F; Tue, 16 May 2023 21:35:39 -0700 (PDT) X-UUID: 447dd3d8f46c11ed9cb5633481061a41-20230517 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zITZHaBffEXHgQvakViptRVDM6YtdJ7FNpbDESp+DO4=; b=rg5FCpR+2adm0lUwGcCji/DWBrJq4vux/x9QDZrGjWMi1LOieoNTeD+YkCjNY0CLn+P8zhmqc6Q7ZYYvxzVQBFqvUw1WSR3pLpHn3e8zwe3FNRLV75PBbK6aMIKV2oLBYv69L6E4KCrEcPNbyFMWDAKFL1iVketgxWtKxJ5FG3I=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.25,REQID:c778c494-0df7-4303-b7d4-3b608b102572,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.25,REQID:c778c494-0df7-4303-b7d4-3b608b102572,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:d5b0ae3,CLOUDID:a95c116c-2f20-4998-991c-3b78627e4938,B ulkID:230517123536FFYEAOTT,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 447dd3d8f46c11ed9cb5633481061a41-20230517 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1071586012; Wed, 17 May 2023 12:35:36 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 17 May 2023 12:35:34 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 17 May 2023 12:35:34 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v12 11/11] arm64: dts: mediatek: mt8195: Add SCP 2nd core Date: Wed, 17 May 2023 12:34:49 +0800 Message-ID: <20230517043449.26352-12-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230517043449.26352-1-tinghan.shen@mediatek.com> References: <20230517043449.26352-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SCC_BODY_TEXT_LINE,T_SPF_TEMPERROR,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766114679246788960?= X-GMAIL-MSGID: =?utf-8?q?1766114679246788960?= Rewrite the MT8195 SCP device node as a cluster and add the SCP 2nd core in it. Since the SCP device node is changed to multi-core structure, enable SCP cluster to enable probing SCP core 0. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 6 +++- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 32 ++++++++++++++----- 2 files changed, 29 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 8ac80a136c37..8addb94a24a1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -962,7 +962,11 @@ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; -&scp { +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { status = "okay"; firmware-name = "mediatek/mt8195/scp.img"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a44aae4ab953..10947b4b4707 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -916,14 +916,30 @@ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; }; - scp: scp@10500000 { - compatible = "mediatek,mt8195-scp"; - reg = <0 0x10500000 0 0x100000>, - <0 0x10720000 0 0xe0000>, - <0 0x10700000 0 0x8000>; - reg-names = "sram", "cfg", "l1tcm"; - interrupts = ; + scp_cluster: scp@10500000 { + compatible = "mediatek,mt8195-scp-dual"; + reg = <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>; + reg-names = "cfg", "l1tcm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x10500000 0x100000>; status = "disabled"; + + scp_c0: scp@0 { + compatible = "mediatek,scp-core"; + reg = <0x0 0xa0000>; + reg-names = "sram"; + interrupts = ; + status = "disabled"; + }; + + scp_c1: scp@a0000 { + compatible = "mediatek,scp-core"; + reg = <0xa0000 0x20000>; + reg-names = "sram"; + interrupts = ; + status = "disabled"; + }; }; scp_adsp: clock-controller@10720000 { @@ -2464,7 +2480,7 @@ <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; interrupts = ; - mediatek,scp = <&scp>; + mediatek,scp = <&scp_c0>; clocks = <&vencsys CLK_VENC_VENC>; clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC>;