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[83.9.3.193]) by smtp.gmail.com with ESMTPSA id u26-20020a056512041a00b004f764716afdsm314395lfk.257.2023.06.20.04.10.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 04:10:47 -0700 (PDT) From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:41 +0200 Subject: [PATCH v4 6/6] drm/msm/a6xx: Fix up GMU region reservations MIME-Version: 1.0 Message-Id: <20230517-topic-a7xx_prep-v4-6-b16f273a91d4@linaro.org> References: <20230517-topic-a7xx_prep-v4-0-b16f273a91d4@linaro.org> In-Reply-To: <20230517-topic-a7xx_prep-v4-0-b16f273a91d4@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , Jonathan Marek , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687259438; l=1342; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yg0CsUYst1MC0yCvcYjryDQIsWMdtt76iHZrZNL17WI=; b=GB3+ryq3V2BFvCAghxWY0vExkzY2tN7nu7hHmqLlYbOvEVQ11xjN4tpj9GRNP9ReuITm1JCY6 e6ZBGvYqexUAuYjiW/9pR7KYSYyhlgIf3t2j677KPojp0fufFkJ2xG6 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769221788357948683?= X-GMAIL-MSGID: =?utf-8?q?1769221788357948683?= Change the order of region allocations to make the addresses match downstream. This shouldn't matter very much, but helps eliminate one more difference when comparing register accesses. Also, make the log region 16K long. That's what it is, unconditionally on A6xx and A7xx. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 55b12a8066ee..d682c1ed48db 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1640,13 +1640,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_memory; } - /* Allocate memory for for the HFI queues */ - ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); + /* Allocate memory for the GMU log region */ + ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log"); if (ret) goto err_memory; - /* Allocate memory for the GMU log region */ - ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0, "log"); + /* Allocate memory for for the HFI queues */ + ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); if (ret) goto err_memory;