| Message ID | 20230517-topic-a7xx_prep-v2-1-5b9daa2b2cf0@linaro.org |
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From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Fri, 19 May 2023 15:29:06 +0200
Subject: [PATCH v2 1/6] drm/msm/a6xx: Add REG_A6XX_GMU_AHB_FENCE_STATUS_CLR
definition
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| Series |
Adreno QoL changes
|
|
Commit Message
Konrad Dybcio
May 19, 2023, 1:29 p.m. UTC
Add a definition of the REG_A6XX_GMU_AHB_FENCE_STATUS_CLR register.
This may be substituted with a mesa header sync after MR22901 is merged.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 9ab15d91aced..fcd9eb53baf8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -425,6 +425,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 +#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314 + #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316