Message ID | 20230516215009.51794-7-tom.zanussi@linux.intel.com |
---|---|
State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y14-20020a17090322ce00b001ade5e66c3csi12518154plg.76.2023.05.16.15.13.08; Tue, 16 May 2023 15:13:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CHYhAkvw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230521AbjEPVu7 (ORCPT <rfc822;peekingduck44@gmail.com> + 99 others); Tue, 16 May 2023 17:50:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231201AbjEPVul (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 16 May 2023 17:50:41 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6F956E96; Tue, 16 May 2023 14:50:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684273826; x=1715809826; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yPVyZBdMFSkLLY+neCVq3Ouyo7u0i8a/xzk2t6QMfsQ=; b=CHYhAkvwbpYrrKxTF9gulG9UwNMYS+HeXRDX+PB5HCmuAfMcfLcTjy62 VdAd+i0zBdnjqQX+NJatsz78JwxxhB0pzSVvDUeBTUbXGIASkui6A0SXg H43gA8FE7HSRJ2b8jFx+DGa/BPrkvca00vuLbOap5MoYRzZO4MxshBSs3 yxTW+GHLfhOihbH8LqQi7D36CbQCpaUrQ3LrQQpjWQDW7oYtMnWf4bPFQ KdrmmskImGLZ9Jdl/13bBfUzUIJj/vI9FQtT8B8nwP1NLOJu0miC0Q445 dMrru3oOQhk/yI5g9GlsVJNo8hf3i1uFejAk6ELEVcn10fztGfhKas8x1 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10712"; a="331961677" X-IronPort-AV: E=Sophos;i="5.99,278,1677571200"; d="scan'208";a="331961677" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2023 14:50:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10712"; a="704564928" X-IronPort-AV: E=Sophos;i="5.99,278,1677571200"; d="scan'208";a="704564928" Received: from fmunozug-mobl1.amr.corp.intel.com (HELO tzanussi-mobl1.intel.com) ([10.212.83.116]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2023 14:50:24 -0700 From: Tom Zanussi <tom.zanussi@linux.intel.com> To: herbert@gondor.apana.org.au, davem@davemloft.net, fenghua.yu@intel.com, vkoul@kernel.org Cc: dave.jiang@intel.com, tony.luck@intel.com, wajdi.k.feghali@intel.com, james.guilford@intel.com, kanchana.p.sridhar@intel.com, giovanni.cabiddu@intel.com, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org Subject: [PATCH v5 06/15] dmaengine: idxd: Add wq private data accessors Date: Tue, 16 May 2023 16:50:00 -0500 Message-Id: <20230516215009.51794-7-tom.zanussi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516215009.51794-1-tom.zanussi@linux.intel.com> References: <20230516215009.51794-1-tom.zanussi@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766090554191595323?= X-GMAIL-MSGID: =?utf-8?q?1766090554191595323?= |
Series |
crypto: Add Intel Analytics Accelerator (IAA) crypto compression driver
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Commit Message
Tom Zanussi
May 16, 2023, 9:50 p.m. UTC
Add the accessors idxd_wq_set_private() and idxd_wq_get_private()
allowing users to set and retrieve a private void * associated with an
idxd_wq.
The private data is stored in the idxd_dev.conf_dev associated with
each idxd_wq.
Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
---
drivers/dma/idxd/idxd.h | 10 ++++++++++
1 file changed, 10 insertions(+)
Comments
On 5/16/23 2:50 PM, Tom Zanussi wrote: > Add the accessors idxd_wq_set_private() and idxd_wq_get_private() > allowing users to set and retrieve a private void * associated with an > idxd_wq. > > The private data is stored in the idxd_dev.conf_dev associated with > each idxd_wq. > > Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/dma/idxd/idxd.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h > index 276b5f9cf967..971daf323655 100644 > --- a/drivers/dma/idxd/idxd.h > +++ b/drivers/dma/idxd/idxd.h > @@ -609,6 +609,16 @@ static inline int idxd_wq_refcount(struct idxd_wq *wq) > return wq->client_count; > }; > > +static inline void idxd_wq_set_private(struct idxd_wq *wq, void *private) > +{ > + dev_set_drvdata(wq_confdev(wq), private); > +} > + > +static inline void *idxd_wq_get_private(struct idxd_wq *wq) > +{ > + return dev_get_drvdata(wq_confdev(wq)); > +} > + > /* > * Intel IAA does not support batch processing. > * The max batch size of device, max batch size of wq and
diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h index 276b5f9cf967..971daf323655 100644 --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h @@ -609,6 +609,16 @@ static inline int idxd_wq_refcount(struct idxd_wq *wq) return wq->client_count; }; +static inline void idxd_wq_set_private(struct idxd_wq *wq, void *private) +{ + dev_set_drvdata(wq_confdev(wq), private); +} + +static inline void *idxd_wq_get_private(struct idxd_wq *wq) +{ + return dev_get_drvdata(wq_confdev(wq)); +} + /* * Intel IAA does not support batch processing. * The max batch size of device, max batch size of wq and