diff mbox series

[v4,4/6] phy: cadence: salvo: add .set_mode API

Message ID 20230516154329.3155031-5-Frank.Li@nxp.com
State New
Headers
Series phy: cadence: salvo: some fixes and workarounds |

Commit Message

Frank Li May 16, 2023, 3:43 p.m. UTC 
  From: Peter Chen <peter.chen@nxp.com>

For NXP platform design, the PHY can't know VBUS well, it causes the FSM
in controller seeing the disconnection at L1 use case. With .set_mode API
introduced, the controller driver could force PHY seeing B Session VALID
when it is at the device mode (VBUS is there), and keep FSM working well.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/phy/cadence/phy-cadence-salvo.c | 29 +++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Vinod Koul May 16, 2023, 4:35 p.m. UTC | #1 
On 16-05-23, 11:43, Frank Li wrote:
> From: Peter Chen <peter.chen@nxp.com>
> 
> For NXP platform design, the PHY can't know VBUS well, it causes the FSM
> in controller seeing the disconnection at L1 use case. With .set_mode API
> introduced, the controller driver could force PHY seeing B Session VALID
> when it is at the device mode (VBUS is there), and keep FSM working well.
> 
> Signed-off-by: Peter Chen <peter.chen@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/phy/cadence/phy-cadence-salvo.c | 29 +++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
> index b9866dc146ce..41616f786321 100644
> --- a/drivers/phy/cadence/phy-cadence-salvo.c
> +++ b/drivers/phy/cadence/phy-cadence-salvo.c
> @@ -92,6 +92,7 @@
>  /* USB2 PHY register definition */
>  #define UTMI_REG15				0xaf
>  #define UTMI_AFE_RX_REG5			0x12
> +#define UTMI_AFE_BC_REG4			0x29
>  
>  /* TB_ADDR_TX_RCVDETSC_CTRL */
>  #define RXDET_IN_P3_32KHZ			BIT(0)
> @@ -105,6 +106,9 @@
>  /* 0us, txvalid is ready just after HS/FS transmitters have powered up */
>  #define TXVALID_GATE_THRESHOLD_HS_0US		(BIT(4) | BIT(5))
>  
> +#define SET_B_SESSION_VALID			(BIT(6) | BIT(5))
> +#define CLR_B_SESSION_VALID			(BIT(6))
> +
>  struct cdns_reg_pairs {
>  	u16 val;
>  	u32 off;
> @@ -124,6 +128,13 @@ struct cdns_salvo_phy {
>  };
>  
>  static const struct of_device_id cdns_salvo_phy_of_match[];
> +static const struct cdns_salvo_data cdns_nxp_salvo_data;
> +
> +static bool cdns_is_nxp_phy(struct cdns_salvo_phy *salvo_phy)
> +{
> +	return salvo_phy->data == &cdns_nxp_salvo_data;
> +}
> +
>  static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg)
>  {
>  	return (u16)readl(salvo_phy->base + offset +
> @@ -273,11 +284,29 @@ static int cdns_salvo_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> +static int cdns_salvo_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> +	struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
> +
> +	if (!cdns_is_nxp_phy(salvo_phy))
> +		return 0;
> +
> +	if (mode == PHY_MODE_INVALID)
> +		cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_BC_REG4,
> +			 CLR_B_SESSION_VALID);
> +	else if (mode == PHY_MODE_USB_DEVICE)
> +		cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_BC_REG4,
> +			 SET_B_SESSION_VALID);

no else?

> +
> +	return 0;

return success even when mode is not handled?

> +}
> +
>  static const struct phy_ops cdns_salvo_phy_ops = {
>  	.init		= cdns_salvo_phy_init,
>  	.power_on	= cdns_salvo_phy_power_on,
>  	.power_off	= cdns_salvo_phy_power_off,
>  	.owner		= THIS_MODULE,
> +	.set_mode	= cdns_salvo_set_mode,
>  };
>  
>  static int cdns_salvo_phy_probe(struct platform_device *pdev)
> -- 
> 2.34.1
diff mbox series

Patch

diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
index b9866dc146ce..41616f786321 100644
--- a/drivers/phy/cadence/phy-cadence-salvo.c
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -92,6 +92,7 @@ 
 /* USB2 PHY register definition */
 #define UTMI_REG15				0xaf
 #define UTMI_AFE_RX_REG5			0x12
+#define UTMI_AFE_BC_REG4			0x29
 
 /* TB_ADDR_TX_RCVDETSC_CTRL */
 #define RXDET_IN_P3_32KHZ			BIT(0)
@@ -105,6 +106,9 @@ 
 /* 0us, txvalid is ready just after HS/FS transmitters have powered up */
 #define TXVALID_GATE_THRESHOLD_HS_0US		(BIT(4) | BIT(5))
 
+#define SET_B_SESSION_VALID			(BIT(6) | BIT(5))
+#define CLR_B_SESSION_VALID			(BIT(6))
+
 struct cdns_reg_pairs {
 	u16 val;
 	u32 off;
@@ -124,6 +128,13 @@  struct cdns_salvo_phy {
 };
 
 static const struct of_device_id cdns_salvo_phy_of_match[];
+static const struct cdns_salvo_data cdns_nxp_salvo_data;
+
+static bool cdns_is_nxp_phy(struct cdns_salvo_phy *salvo_phy)
+{
+	return salvo_phy->data == &cdns_nxp_salvo_data;
+}
+
 static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg)
 {
 	return (u16)readl(salvo_phy->base + offset +
@@ -273,11 +284,29 @@  static int cdns_salvo_phy_power_off(struct phy *phy)
 	return 0;
 }
 
+static int cdns_salvo_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+	struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
+
+	if (!cdns_is_nxp_phy(salvo_phy))
+		return 0;
+
+	if (mode == PHY_MODE_INVALID)
+		cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_BC_REG4,
+			 CLR_B_SESSION_VALID);
+	else if (mode == PHY_MODE_USB_DEVICE)
+		cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_BC_REG4,
+			 SET_B_SESSION_VALID);
+
+	return 0;
+}
+
 static const struct phy_ops cdns_salvo_phy_ops = {
 	.init		= cdns_salvo_phy_init,
 	.power_on	= cdns_salvo_phy_power_on,
 	.power_off	= cdns_salvo_phy_power_off,
 	.owner		= THIS_MODULE,
+	.set_mode	= cdns_salvo_set_mode,
 };
 
 static int cdns_salvo_phy_probe(struct platform_device *pdev)