diff mbox series

[6/9] ASoC: amd: ps: add pm ops support for soundwire dma driver

Message ID 20230516103543.2515097-7-Vijendar.Mukunda@amd.com
State New
Headers
Series [1/9] ASoC: amd: ps: create platform devices based on acp config |

Commit Message

Mukunda,Vijendar May 16, 2023, 10:35 a.m. UTC 
  Add support pm ops support for soundwire dma driver.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 sound/soc/amd/ps/ps-sdw-dma.c | 86 +++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)
diff mbox series

Patch

diff --git a/sound/soc/amd/ps/ps-sdw-dma.c b/sound/soc/amd/ps/ps-sdw-dma.c
index 5002ef16d980..8901a52f7498 100644
--- a/sound/soc/amd/ps/ps-sdw-dma.c
+++ b/sound/soc/amd/ps/ps-sdw-dma.c
@@ -12,6 +12,7 @@ 
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 #include <sound/soc-dai.h>
+#include <linux/pm_runtime.h>
 #include <linux/soundwire/sdw_amd.h>
 #include "acp63.h"
 
@@ -102,6 +103,29 @@  static const struct snd_pcm_hardware acp63_sdw_hardware_capture = {
 	.periods_max = SDW_CAPTURE_MAX_NUM_PERIODS,
 };
 
+static void acp63_enable_disable_sdw_dma_interrupts(void __iomem *acp_base, bool enable)
+{
+	u32 ext_intr_cntl, ext_intr_cntl1;
+	u32 irq_mask = ACP_SDW_DMA_IRQ_MASK;
+	u32 irq_mask1 = ACP_P1_SDW_DMA_IRQ_MASK;
+
+	if (enable) {
+		ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
+		ext_intr_cntl |= irq_mask;
+		writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL);
+		ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1);
+		ext_intr_cntl1 |= irq_mask1;
+		writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
+	} else {
+		ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
+		ext_intr_cntl &= ~irq_mask;
+		writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL);
+		ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1);
+		ext_intr_cntl1 &= ~irq_mask1;
+		writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
+	}
+}
+
 static void acp63_config_dma(struct sdw_dma_stream_instance *sdw_ins, void __iomem *acp_base,
 			     u32 stream_id)
 {
@@ -470,13 +494,75 @@  static int acp63_sdw_platform_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "Fail to register sdw dma component\n");
 		return -ENODEV;
 	}
+	pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_allow(&pdev->dev);
+	return 0;
+}
+
+static int acp63_sdw_platform_remove(struct platform_device *pdev)
+{
+	pm_runtime_disable(&pdev->dev);
+	return 0;
+}
+
+static int __maybe_unused acp63_sdw_pcm_resume(struct device *dev)
+{
+	struct sdw_dma_dev_data *sdw_data;
+	struct sdw_dma_stream_instance *sdw_ins;
+	struct snd_pcm_runtime *runtime;
+	u32 period_bytes, buf_size, water_mark_size_reg;
+	int ret;
+	int index;
+
+	sdw_data = dev_get_drvdata(dev);
+	for (index = 0; index < ACP63_SDW0_DMA_MAX_STREAMS; index++) {
+		if (sdw_data->sdw0_dma_stream[index] &&
+		    sdw_data->sdw0_dma_stream[index]->runtime) {
+			water_mark_size_reg = sdw0_dma_ring_buf_reg[index].water_mark_size_reg;
+			runtime = sdw_data->sdw0_dma_stream[index]->runtime;
+			sdw_ins = runtime->private_data;
+			period_bytes = frames_to_bytes(runtime, runtime->period_size);
+			buf_size = frames_to_bytes(runtime, runtime->buffer_size);
+			acp63_config_dma(sdw_ins, sdw_data->acp_base, index);
+			ret = acp63_configure_sdw_ringbuffer(sdw_data->acp_base, index,
+							     buf_size, ACP_SDW0);
+			if (ret)
+				return ret;
+			writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
+		}
+	}
+	for (index = 0; index < ACP63_SDW1_DMA_MAX_STREAMS; index++) {
+		if (sdw_data->sdw1_dma_stream[index] &&
+		    sdw_data->sdw1_dma_stream[index]->runtime) {
+			water_mark_size_reg = sdw1_dma_ring_buf_reg[index].water_mark_size_reg;
+			runtime = sdw_data->sdw1_dma_stream[index]->runtime;
+			sdw_ins = runtime->private_data;
+			period_bytes = frames_to_bytes(runtime, runtime->period_size);
+			buf_size = frames_to_bytes(runtime, runtime->buffer_size);
+			acp63_config_dma(sdw_ins, sdw_data->acp_base, index);
+			ret = acp63_configure_sdw_ringbuffer(sdw_data->acp_base, index,
+							     buf_size, ACP_SDW1);
+			if (ret)
+				return ret;
+			writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
+		}
+	}
+	acp63_enable_disable_sdw_dma_interrupts(sdw_data->acp_base, true);
 	return 0;
 }
 
+static const struct dev_pm_ops acp63_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(NULL, acp63_sdw_pcm_resume)
+};
+
 static struct platform_driver acp63_sdw_dma_driver = {
 	.probe = acp63_sdw_platform_probe,
+	.remove = acp63_sdw_platform_remove,
 	.driver = {
 		.name = "amd_ps_sdw_dma",
+		.pm = &acp63_pm_ops,
 	},
 };