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[2620:137:e000::1:20]) by mx.google.com with ESMTP id je20-20020a170903265400b001ae001e8bc9si4835511plb.188.2023.05.15.04.17.48; Mon, 15 May 2023 04:18:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240784AbjEOKxo (ORCPT + 99 others); Mon, 15 May 2023 06:53:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235490AbjEOKxm (ORCPT ); Mon, 15 May 2023 06:53:42 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 912BC10CA for ; Mon, 15 May 2023 03:53:41 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C59242F4; Mon, 15 May 2023 03:54:25 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.70.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 256023F7BD; Mon, 15 May 2023 03:53:37 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org Subject: [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1 Date: Mon, 15 May 2023 16:23:28 +0530 Message-Id: <20230515105328.239204-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765958729015424486?= X-GMAIL-MSGID: =?utf-8?q?1765958729015424486?= This disables EL2 traps for BRBE instructions executed in EL1. This would enable BRBE to be configured and used successfully in the guest kernel. While here, this updates Documentation/arm64/booting.rst as well. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- This patch applies on v6.4-rc2 Changes in V2: - Updated Documentation/arm64/booting.rst Changes in V1: https://lore.kernel.org/all/20230324055127.2228330-1-anshuman.khandual@arm.com/ Documentation/arm64/booting.rst | 8 ++++++++ arch/arm64/include/asm/el2_setup.h | 10 ++++++++++ 2 files changed, 18 insertions(+) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index ffeccdd6bdac..cb9e151f6928 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -379,6 +379,14 @@ Before jumping into the kernel, the following conditions must be met: - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. + For CPUs with the Branch Record Buffer Extension (FEAT_BRBE): + + - If the kernel is entered at EL1 and EL2 is present: + + - HFGITR_EL2.nBRBINJ (bit 55) must be initialised to 0b1. + + - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 037724b19c5c..06bf321a17be 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -161,6 +161,16 @@ msr_s SYS_HFGWTR_EL2, x0 msr_s SYS_HFGITR_EL2, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 + cbz x1, .Lskip_brbe_\@ + + mov x0, xzr + orr x0, x0, #HFGITR_EL2_nBRBIALL + orr x0, x0, #HFGITR_EL2_nBRBINJ + msr_s SYS_HFGITR_EL2, x0 + +.Lskip_brbe_\@: mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 cbz x1, .Lskip_fgt_\@