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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t17-20020a639551000000b0050fad5c9f36si15363598pgn.354.2023.05.15.00.14.28; Mon, 15 May 2023 00:14:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=jwdIjSu9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234266AbjEOGxH (ORCPT + 99 others); Mon, 15 May 2023 02:53:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240313AbjEOGwl (ORCPT ); Mon, 15 May 2023 02:52:41 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9D4B1A6 for ; Sun, 14 May 2023 23:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684133530; x=1715669530; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dP4H8fKlSakREtkAjsQMf+bbkPa/9U74r38JynphR7o=; b=jwdIjSu91vfWInVMxJLeGaYGs2yJFvCDK3eUbiimzWAtlmcNJT57oXOu Sh0biYabg2NhxmRmMlkzV/aEDF2Kr1QpeVg1MdfRUomXfZWIPPiYPPAP/ SsB85NbI2P1JqVnw5OrSSAFRdDl+Wb4qIKoIYEUtjwct7YhrpzugpNa01 IDxWT7AJCWu8ujJnOQfuLpCIM6kbrrP9Ygfa0Tu9dCZL2aMgpAJRK42pr CzHcEsxmmTK3c32Kaq7GQ8dKxRt7sISuoea52IBlFa9IXEu8IybmX+GBp wJuzThexOGwpRkp6tkkBV7zCmWWB7IomaPCR+L3VjXjVNWzEa59fIVov9 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="349966535" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="349966535" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 23:51:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="694908779" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="694908779" Received: from bard-ubuntu.sh.intel.com ([10.239.185.57]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 23:51:08 -0700 From: Bard Liao To: alsa-devel@alsa-project.org, vkoul@kernel.org, broonie@kernel.org, tiwai@suse.de Cc: linux-kernel@vger.kernel.org, vinod.koul@linaro.org, pierre-louis.bossart@linux.intel.com, bard.liao@intel.com Subject: [PATCH v2 21/26] soundwire: intel_ace2x: add pre/post bank switch callbacks Date: Mon, 15 May 2023 15:10:37 +0800 Message-Id: <20230515071042.2038-22-yung-chuan.liao@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230515071042.2038-1-yung-chuan.liao@linux.intel.com> References: <20230515071042.2038-1-yung-chuan.liao@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765943417657167435?= X-GMAIL-MSGID: =?utf-8?q?1765943417657167435?= From: Pierre-Louis Bossart The .pre_ and .post_switch callbacks are mandatory. Signed-off-by: Pierre-Louis Bossart Reviewed-by: Rander Wang Reviewed-by: Ranjani Sridharan Signed-off-by: Bard Liao --- drivers/soundwire/intel_ace2x.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/soundwire/intel_ace2x.c b/drivers/soundwire/intel_ace2x.c index 65deb4345354..1be0bea5f40f 100644 --- a/drivers/soundwire/intel_ace2x.c +++ b/drivers/soundwire/intel_ace2x.c @@ -378,6 +378,9 @@ const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops = { .shim_check_wake = intel_shim_check_wake, .shim_wake = intel_shim_wake, + .pre_bank_switch = intel_pre_bank_switch, + .post_bank_switch = intel_post_bank_switch, + .sync_arm = intel_sync_arm, .sync_go_unlocked = intel_sync_go_unlocked, .sync_go = intel_sync_go,