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[V6,02/21] platform/surface: Disable for RISC-V

Message ID	20230515054928.2079268-3-sunilvl@ventanamicro.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Sunil V L <sunilvl@ventanamicro.com> To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, "Rafael J . Wysocki" <rafael@kernel.org>, Len Brown <lenb@kernel.org>, Sunil V L <sunilvl@ventanamicro.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Weili Qian <qianweili@huawei.com>, Zhou Wang <wangzhou1@hisilicon.com>, Herbert Xu <herbert@gondor.apana.org.au>, "David S . Miller" <davem@davemloft.net>, Marc Zyngier <maz@kernel.org>, Maximilian Luz <luzmaximilian@gmail.com>, Hans de Goede <hdegoede@redhat.com>, Mark Gross <markgross@kernel.org>, Nathan Chancellor <nathan@kernel.org>, Nick Desaulniers <ndesaulniers@google.com>, Tom Rix <trix@redhat.com> Subject: [PATCH V6 02/21] platform/surface: Disable for RISC-V Date: Mon, 15 May 2023 11:19:09 +0530 Message-Id: <20230515054928.2079268-3-sunilvl@ventanamicro.com> In-Reply-To: <20230515054928.2079268-1-sunilvl@ventanamicro.com> References: <20230515054928.2079268-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add basic ACPI support for RISC-V \| [V6,00/21] Add basic ACPI support for RISC-V [V6,01/21] riscv: move sbi_init() earlier before jump_label_init() [V6,02/21] platform/surface: Disable for RISC-V [V6,03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang [V6,04/21] ACPI: tables: Print RINTC information when MADT is parsed [V6,05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V [V6,06/21] RISC-V: Add support to build the ACPI core [V6,07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid [V6,08/21] RISC-V: Add ACPI initialization in setup_arch() [V6,09/21] RISC-V: ACPI: Cache and retrieve the RINTC structure [V6,10/21] drivers/acpi: RISC-V: Add RHCT related code [V6,11/21] RISC-V: smpboot: Create wrapper setup_smp() [V6,12/21] RISC-V: smpboot: Add ACPI support in setup_smp() [V6,13/21] RISC-V: only iterate over possible CPUs in ISA string parser [V6,14/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() [V6,15/21] RISC-V: cpu: Enable cpuinfo for ACPI systems [V6,16/21] irqchip/riscv-intc: Add ACPI support [V6,17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() [V6,18/21] clocksource/timer-riscv: Add ACPI support [V6,19/21] RISC-V: time.c: Add ACPI support for time_init() [V6,20/21] RISC-V: Enable ACPI in defconfig [V6,21/21] MAINTAINERS: Add entry for drivers/acpi/riscv

Commit Message

Sunil V L May 15, 2023, 5:49 a.m. UTC

  With CONFIG_ACPI enabled for RISC-V, this driver gets enabled
in allmodconfig build. However, RISC-V doesn't support sub-word
atomics which is used by this driver and hence allmodconfig
build will fail.

There is currently no plan to support this driver for RISC-V. So,
disable this driver for RISC-V even when ACPI is enabled.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Maximilian Luz <luzmaximilian@gmail.com>
---
 drivers/platform/surface/aggregator/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/drivers/platform/surface/aggregator/Kconfig b/drivers/platform/surface/aggregator/Kconfig
index c114f9dd5fe1..88afc38ffdc5 100644
--- a/drivers/platform/surface/aggregator/Kconfig
+++ b/drivers/platform/surface/aggregator/Kconfig
@@ -4,7 +4,7 @@ 
 menuconfig SURFACE_AGGREGATOR
 	tristate "Microsoft Surface System Aggregator Module Subsystem and Drivers"
 	depends on SERIAL_DEV_BUS
-	depends on ACPI
+	depends on ACPI && !RISCV
 	select CRC_CCITT
 	help
 	  The Surface System Aggregator Module (Surface SAM or SSAM) is an