From patchwork Fri May 12 02:20:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 92924 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp4801833vqo; Thu, 11 May 2023 19:25:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4PYLyBTsxftqQeZLimzgFltIjYA+7ZHzWNIYN2ZodU3kydrPuFw9U2ZGNV4RzzBE2WcZ3u X-Received: by 2002:a05:6a21:32a8:b0:100:60f3:2975 with SMTP id yt40-20020a056a2132a800b0010060f32975mr21361070pzb.4.1683858356623; Thu, 11 May 2023 19:25:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683858356; cv=none; d=google.com; s=arc-20160816; b=S0IPfdBxCxxyHePRr7gJBsG3jDNsoWQyMZDK8Mzt+3N6JnwLjLiTnWC3EmioRjJUnQ g355t3paTW6v+f7lFkSUa6vzXk393bjahtC3HshXX6ykOM7P2ivlSoH1KY3Gcp46W7VE 3mi+53gVE6eUOI1C9LcYy/pIC1Il4G+06hpEXgp+Mu+Sj+f62/kWwS0ozglN8wp/BHIQ W5CWld8/xia9X8Zw9PhsgEttmJpt9+UEy2ivU0Rh5l9USdzrjRPTtDM/rVpqsZ1H0W6r hfT+aP2VqzwhtGK7U8WTcPX+BTCdlm9yxsTTXpFh9c9k3nNaBLwIR6LJ3B8xtPIT/eQV 4f4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=E1D/hT86jY4a9M+Oep7LH+vCGrSRWz0dsvCeYPMH5DY=; b=ThtQcs0E6sjrCDHoDWT6fCImEHHEl2l2gv0dEPqAUtz3W1JHpAmqxOivFlM5zQ6KO+ vqWX580TlHkr39t/AnsY/KPpJcyXfa9Wez9QevQ2Q/h7We5yeAtWtsRfTwi88xRxwAUN 3CDJomopalE/7kVPZ99KPliKzt7mxbxlLIIdL4BZH4w4lhV8rnBkr0dCZBOmj//Z0FBK xbWTux3x1aSOptfjkzakP6fBcRpGd/24rJuP9OTfE/YrL8O8J+3g/yRcbhU3y+o5BQzv 4qJACN2cN6Ova5ON2Xn/dDSRet/zTH2Icix/phVyk8taZN6cet6c1D/IR6exFbmM5Fbv UfMw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u16-20020a63b550000000b0053072cbae67si3633861pgo.379.2023.05.11.19.25.42; Thu, 11 May 2023 19:25:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239839AbjELCWj convert rfc822-to-8bit (ORCPT + 99 others); Thu, 11 May 2023 22:22:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239780AbjELCWW (ORCPT ); Thu, 11 May 2023 22:22:22 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B90365BA5; Thu, 11 May 2023 19:22:20 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 00D1E817A; Fri, 12 May 2023 10:22:14 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 12 May 2023 10:22:13 +0800 Received: from localhost.localdomain (113.72.146.187) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 12 May 2023 10:22:12 +0800 From: Xingyu Wu To: , , "Michael Turquette" , Stephen Boyd , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , "Emil Renner Berthing" CC: Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , William Qiu , , Subject: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Date: Fri, 12 May 2023 10:20:30 +0800 Message-ID: <20230512022036.97987-2-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230512022036.97987-1-xingyu.wu@starfivetech.com> References: <20230512022036.97987-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.146.187] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765653459935625694?= X-GMAIL-MSGID: =?utf-8?q?1765653459935625694?= Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xingyu Wu --- .../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++ 2 files changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml new file mode 100644 index 000000000000..8aa8c7b8e42f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PLL Clock Generator + +description: + This PLL are high speed, low jitter frequency synthesizers in JH7110. + Each PLL clocks work in integer mode or fraction mode by some dividers, + and the configuration registers and dividers are set in several syscon + registers. So pll node should be a child of SYS-SYSCON node. + The formula for calculating frequency is that, + Fvco = Fref * (NI + NF) / M / Q1 + +maintainers: + - Xingyu Wu + +properties: + compatible: + const: starfive,jh7110-pll + + clocks: + maxItems: 1 + description: Main Oscillator (24 MHz) + + '#clock-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + pll-clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..086a6ddcf380 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -6,6 +6,12 @@ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_CLK_PLL0_OUT 0 +#define JH7110_CLK_PLL1_OUT 1 +#define JH7110_CLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1