diff mbox series

[v3,02/10] iommu/vt-d: Extend dmar_domain to support nested domain

Message ID 20230511145110.27707-3-yi.l.liu@intel.com
State New
Headers
Series Add Intel VT-d nested translation |

Commit Message

Yi Liu May 11, 2023, 2:51 p.m. UTC 
  From: Lu Baolu <baolu.lu@linux.intel.com>

The nested domain fields are exclusive to those that used for a DMA
remapping domain. Use union to avoid memory waste.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
---
 drivers/iommu/intel/iommu.h | 35 +++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)

Comments

Tian, Kevin May 24, 2023, 7:02 a.m. UTC | #1 
> From: Liu, Yi L <yi.l.liu@intel.com>
> Sent: Thursday, May 11, 2023 10:51 PM
> 
> From: Lu Baolu <baolu.lu@linux.intel.com>
> 
> The nested domain fields are exclusive to those that used for a DMA
> remapping domain. Use union to avoid memory waste.
> 
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> Signed-off-by: Yi Liu <yi.l.liu@intel.com>
> ---
>  drivers/iommu/intel/iommu.h | 35 +++++++++++++++++++++++++++++------
>  1 file changed, 29 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h
> index 1c5e1d88862b..e818520f4068 100644
> --- a/drivers/iommu/intel/iommu.h
> +++ b/drivers/iommu/intel/iommu.h
> @@ -596,15 +596,38 @@ struct dmar_domain {
>  	spinlock_t lock;		/* Protect device tracking lists */
>  	struct list_head devices;	/* all devices' list */
> 
> -	struct dma_pte	*pgd;		/* virtual address */
> -	int		gaw;		/* max guest address width */
> -
> -	/* adjusted guest address width, 0 is level 2 30-bit */
> -	int		agaw;
>  	int		iommu_superpage;/* Level of superpages supported:
>  					   0 == 4KiB (no superpages), 1 ==
> 2MiB,
>  					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
> -	u64		max_addr;	/* maximum mapped address */
> +	union {
> +		/* DMA remapping domain */
> +		struct {
> +			/* virtual address */
> +			struct dma_pte	*pgd;
> +			/* max guest address width */
> +			int		gaw;
> +			/*
> +			 * adjusted guest address width:
> +			 *   0: level 2 30-bit
> +			 *   1: level 3 39-bit
> +			 *   2: level 4 48-bit
> +			 *   3: level 5 57-bit
> +			 */
> +			int		agaw;
> +			/* maximum mapped address */
> +			u64		max_addr;
> +		};

what about 'nid'?

> +
> +		/* Nested user domain */
> +		struct {
> +			/* 2-level page table the user domain nested */

/* parent page table which the user domain is nested on */

> +			struct dmar_domain *s2_domain;
> +			/* user page table pointer (in GPA) */
> +			unsigned long s1_pgtbl;
> +			/* page table attributes */
> +			struct iommu_hwpt_intel_vtd s1_cfg;
> +		};
> +	};
> 
>  	struct iommu_domain domain;	/* generic domain data structure for
>  					   iommu core */
> --
> 2.34.1
Baolu Lu May 26, 2023, 2:56 a.m. UTC | #2 
On 5/24/23 3:02 PM, Tian, Kevin wrote:
>> From: Liu, Yi L<yi.l.liu@intel.com>
>> Sent: Thursday, May 11, 2023 10:51 PM
>>
>> From: Lu Baolu<baolu.lu@linux.intel.com>
>>
>> The nested domain fields are exclusive to those that used for a DMA
>> remapping domain. Use union to avoid memory waste.
>>
>> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
>> Signed-off-by: Yi Liu<yi.l.liu@intel.com>
>> ---
>>   drivers/iommu/intel/iommu.h | 35 +++++++++++++++++++++++++++++------
>>   1 file changed, 29 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h
>> index 1c5e1d88862b..e818520f4068 100644
>> --- a/drivers/iommu/intel/iommu.h
>> +++ b/drivers/iommu/intel/iommu.h
>> @@ -596,15 +596,38 @@ struct dmar_domain {
>>   	spinlock_t lock;		/* Protect device tracking lists */
>>   	struct list_head devices;	/* all devices' list */
>>
>> -	struct dma_pte	*pgd;		/* virtual address */
>> -	int		gaw;		/* max guest address width */
>> -
>> -	/* adjusted guest address width, 0 is level 2 30-bit */
>> -	int		agaw;
>>   	int		iommu_superpage;/* Level of superpages supported:
>>   					   0 == 4KiB (no superpages), 1 ==
>> 2MiB,
>>   					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
>> -	u64		max_addr;	/* maximum mapped address */
>> +	union {
>> +		/* DMA remapping domain */
>> +		struct {
>> +			/* virtual address */
>> +			struct dma_pte	*pgd;
>> +			/* max guest address width */
>> +			int		gaw;
>> +			/*
>> +			 * adjusted guest address width:
>> +			 *   0: level 2 30-bit
>> +			 *   1: level 3 39-bit
>> +			 *   2: level 4 48-bit
>> +			 *   3: level 5 57-bit
>> +			 */
>> +			int		agaw;
>> +			/* maximum mapped address */
>> +			u64		max_addr;
>> +		};
> what about 'nid'?


"nid" represents which NUMA node should we allocate pages from for this
domain. It's updated every time when a domain is attached/detached
to/from a device or pasid.

Generally speaking, "nid" is common for all types of domain. But in this
case, only a DMA remapping domain has a need to allocate pages. I intend
to keep it as it for now. There's more cleanup rooms if we limit it only
for DMA remapping domain.

Best regards,
baolu
diff mbox series

Patch

diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h
index 1c5e1d88862b..e818520f4068 100644
--- a/drivers/iommu/intel/iommu.h
+++ b/drivers/iommu/intel/iommu.h
@@ -596,15 +596,38 @@  struct dmar_domain {
 	spinlock_t lock;		/* Protect device tracking lists */
 	struct list_head devices;	/* all devices' list */
 
-	struct dma_pte	*pgd;		/* virtual address */
-	int		gaw;		/* max guest address width */
-
-	/* adjusted guest address width, 0 is level 2 30-bit */
-	int		agaw;
 	int		iommu_superpage;/* Level of superpages supported:
 					   0 == 4KiB (no superpages), 1 == 2MiB,
 					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
-	u64		max_addr;	/* maximum mapped address */
+	union {
+		/* DMA remapping domain */
+		struct {
+			/* virtual address */
+			struct dma_pte	*pgd;
+			/* max guest address width */
+			int		gaw;
+			/*
+			 * adjusted guest address width:
+			 *   0: level 2 30-bit
+			 *   1: level 3 39-bit
+			 *   2: level 4 48-bit
+			 *   3: level 5 57-bit
+			 */
+			int		agaw;
+			/* maximum mapped address */
+			u64		max_addr;
+		};
+
+		/* Nested user domain */
+		struct {
+			/* 2-level page table the user domain nested */
+			struct dmar_domain *s2_domain;
+			/* user page table pointer (in GPA) */
+			unsigned long s1_pgtbl;
+			/* page table attributes */
+			struct iommu_hwpt_intel_vtd s1_cfg;
+		};
+	};
 
 	struct iommu_domain domain;	/* generic domain data structure for
 					   iommu core */