From patchwork Thu May 11 13:07:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 92568 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp4362816vqo; Thu, 11 May 2023 06:15:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4dlC9BCxBIBcW/XHW2Kb+NgwmPg2XtG6LKDUTSWNTQJ7KoSCglAsD/ycsahlAIXGLM8gx3 X-Received: by 2002:a05:6a20:3c8b:b0:103:e735:d157 with SMTP id b11-20020a056a203c8b00b00103e735d157mr2467682pzj.59.1683810947163; Thu, 11 May 2023 06:15:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683810947; cv=none; d=google.com; s=arc-20160816; b=rtxpMJWfLbBJb5xCN2LN++h+igKmWDTswTazRAXio1KStM9qJA8EolBiaymuy/sW0U aHyu7UhNZ7vcD9LTsKTBA6PM/1HCnfgIUIdgc6HP6bdQBIQ2QJCgPhM91Io4JyNRm9lG tg5BgoRwJyrZXsPIhf4bc5kbsAckCn3TcpWIns7hdU6dKncsaLut6q0zt4Hj1BtkA+wh dRoG0SQsldkemYdqqAHlE//ND3zvmrxD6AyfvLi8aFKNBDJyAlWQFwPb0/KVLDtWP6jE MQ+LomgQnaLpLbZTjHXobPUfizctedirbvB/GNyuqkGGxW5N3AgD8eMK8wT4xmpStfQK dvWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=McbrDClLAa4Ffqe7gNkDhk2tAuCUOtWI2oWivkQHYZ0=; b=dzdeigiWpoHgtpCTCBQ6Y+QOQdxWT5j6c3Ag3GBKAEKvkzl5E872jZmrwoldzTr751 8kW9F0mrjxr/tjVmoSCu9RNVZYUMnP1OeC82b9JqrSrs7rzmwBiNza3uG2tV+5MXyAIw KvpSzRLjkj2XyDMoDfTrWRJvukS8wk1MsJPbY6A6Z/5iCFKPUSfj5dSulIFadOqo2vG9 jkOw/cv9ETminzvMVQghanG+emG4eclqaDnDj5WKkKDAlQ2i0ZKgBx3lIelLEyVuS6Zn U2Lx2vzhUuNG6JxXxAhd0sGknRIjy6jMIdId/8mFJFN2nBtqcVOxoR/zepjuiGVaaVVH v8Yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=lJiBA6TI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a28-20020a637f1c000000b0051bb433f5bbsi6932510pgd.386.2023.05.11.06.15.31; Thu, 11 May 2023 06:15:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=lJiBA6TI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237999AbjEKNIK (ORCPT + 99 others); Thu, 11 May 2023 09:08:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232578AbjEKNIE (ORCPT ); Thu, 11 May 2023 09:08:04 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EAF340C2; Thu, 11 May 2023 06:08:01 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34BBlKmr030407; Thu, 11 May 2023 13:07:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=McbrDClLAa4Ffqe7gNkDhk2tAuCUOtWI2oWivkQHYZ0=; b=lJiBA6TIknFsBZC+vOafbutt8WQBNpMaRFIvOD4CeTM2cNAw/1rHNYxPRbOfTkcC4+iU 8dteZHAoFtCD7klXoYVDO9EN1YVgieshSOFr6EQv10fcYoddnVoucDd8H+UyYHHWtXcx E5kDrspbxymkP4aHE7B/lU+kr/pnY0NjkxTj8Wd44rS5LYsgtcwOr4VBsFg7QYkbVUmm rOPmu+zSXk78UpzrJpxSNWi89f8DzfsCWQBP35ygfArL4uBLiwo/l5jdy8vjUbA5QBBy 50prH2qGLc9OBrSX5vAsoDqoTMdU14b4SHmXlngJAEN7Jr94HmwEpGcwYm+bqURGq/lT aQ== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qgj141unu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 May 2023 13:07:41 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34BD7ZEY013394; Thu, 11 May 2023 13:07:38 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3qdy5bq6rd-1; Thu, 11 May 2023 13:07:38 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34BD7bKx013422; Thu, 11 May 2023 13:07:37 GMT Received: from mdalam-linux.qualcomm.com (mdalam-linux.qualcomm.com [10.201.2.71]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 34BD7b7a013421; Thu, 11 May 2023 13:07:37 +0000 Received: by mdalam-linux.qualcomm.com (Postfix, from userid 466583) id E539112010C1; Thu, 11 May 2023 18:37:36 +0530 (IST) From: Md Sadre Alam To: mani@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_mdalam@quicinc.com, 0000-cover-letter.patch@qualcomm.com Subject: [PATCH 3/5] mtd: rawnand: qcom: Add support for param_page read exec_ops Date: Thu, 11 May 2023 18:37:28 +0530 Message-Id: <20230511130730.28689-3-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230511130730.28689-1-quic_mdalam@quicinc.com> References: <20230511130730.28689-1-quic_mdalam@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 09sp2Z-sivQ2v3qbMasON0aPBUmVwPOT X-Proofpoint-ORIG-GUID: 09sp2Z-sivQ2v3qbMasON0aPBUmVwPOT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-11_09,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305110113 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765603747982317899?= X-GMAIL-MSGID: =?utf-8?q?1765603747982317899?= This change will add exec_ops for PARAM_PAGE_READ command. Co-developed-by: Sricharan Ramabadhran Signed-off-by: Sricharan Ramabadhran Signed-off-by: Md Sadre Alam --- drivers/mtd/nand/raw/qcom_nandc.c | 91 ++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index d2f2a8971907..8717d5086f80 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -3086,7 +3086,96 @@ static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_su static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_subop *subop) { - return 0; + struct qcom_nand_host *host = to_qcom_nand_host(chip); + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct qcom_op q_op; + const struct nand_op_instr *instr = NULL; + unsigned int op_id = 0; + unsigned int len = 0; + int ret = 0; + + qcom_parse_instructions(chip, subop, &q_op); + + q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; + + pre_command(host, NAND_CMD_PARAM); + /* + * NAND_CMD_PARAM is called before we know much about the FLASH chip + * in use. we configure the controller to perform a raw read of 512 + * bytes to read onfi params + */ + if (nandc->props->qpic_v2) + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); + else + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); + + nandc_set_reg(chip, NAND_ADDR0, 0); + nandc_set_reg(chip, NAND_ADDR1, 0); + nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE + | 512 << UD_SIZE_BYTES + | 5 << NUM_ADDR_CYCLES + | 0 << SPARE_SIZE_BYTES); + nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES + | 0 << CS_ACTIVE_BSY + | 17 << BAD_BLOCK_BYTE_NUM + | 1 << BAD_BLOCK_IN_SPARE_AREA + | 2 << WR_RD_BSY_GAP + | 0 << WIDE_FLASH + | 1 << DEV0_CFG1_ECC_DISABLE); + if (!nandc->props->qpic_v2) + nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); + + /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */ + if (!nandc->props->qpic_v2) { + nandc_set_reg(chip, NAND_DEV_CMD_VLD, + (nandc->vld & ~READ_START_VLD)); + nandc_set_reg(chip, NAND_DEV_CMD1, + (nandc->cmd1 & ~(0xFF << READ_ADDR)) + | NAND_CMD_PARAM << READ_ADDR); + } + + nandc_set_reg(chip, NAND_EXEC_CMD, 1); + + if (!nandc->props->qpic_v2) { + nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1); + nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); + } + + nandc_set_read_loc(chip, 0, 0, 0, 512, 1); + + if (!nandc->props->qpic_v2) { + write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); + write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); + } + + nandc->buf_count = 512; + memset(nandc->data_buffer, 0xff, nandc->buf_count); + + config_nand_single_cw_page_read(chip, false, 0); + + read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, + nandc->buf_count, 0); + + /* restore CMD1 and VLD regs */ + if (!nandc->props->qpic_v2) { + write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); + write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); + } + + ret = submit_descs(nandc); + if (ret) + dev_err(nandc->dev, "failure in sbumitting param page descriptor\n"); + + free_descs(nandc); + + ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); + + instr = q_op.data_instr; + op_id = q_op.data_instr_idx; + len = nand_subop_get_data_len(subop, op_id); + memcpy(instr->ctx.data.buf.in, nandc->data_buffer, len); + + return ret; } static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subop *subop)