[v1,2/5] iommu/arm-smmu-v3: Add has_stage1 field
Commit Message
Inferring the state of the STE based on attached domains becomes tricker
when multiple domains can be attached to a master on different PASIDs.
The new field allows the smmu driver to directly query the state of the
STE (S1 present, S2 present, neither) instead of inferring it from the
attached domain.
Signed-off-by: Michael Shavit <mshavit@google.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 +++++++--------------
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +
2 files changed, 8 insertions(+), 15 deletions(-)
@@ -980,9 +980,9 @@ static void arm_smmu_sync_cd(struct arm_smmu_master *master,
};
/*
- * There's nothing to sync if the STE isn't valid yet.
+ * There's nothing to sync if stage 1 hasn't been installed yet.
*/
- if (!master->domain)
+ if (!master->has_stage1)
return;
cmds.num = 0;
@@ -1278,20 +1278,11 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
.sid = sid,
},
};
- struct iommu_domain *domain = NULL;
-
if (master) {
smmu = master->smmu;
- if (master->domain)
- domain = &master->domain->domain;
- }
- if (domain) {
- if (domain->type != IOMMU_DOMAIN_IDENTITY) {
- if (master->s2_cfg)
- s2_cfg = master->s2_cfg;
- else
- s1_cfg = &master->s1_cfg;
- }
+ if (master->has_stage1)
+ s1_cfg = &master->s1_cfg;
+ s2_cfg = master->s2_cfg;
}
if (val & STRTAB_STE_0_V) {
@@ -2367,9 +2358,9 @@ static void arm_smmu_detach_dev(struct arm_smmu_master *master)
list_del(&master->domain_head);
spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
- master->domain = NULL;
master->ats_enabled = false;
master->s2_cfg = NULL;
+ master->has_stage1 = false;
/*
* Note that this will end up calling arm_smmu_sync_cd() even though
* we're about to destroy the entire STE anyways. This is ok because
@@ -2426,6 +2417,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
* This isn't an issue because the STE hasn't been installed yet.
*/
if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
+ master->has_stage1 = true;
ret = arm_smmu_write_ctx_desc(master, 0, &smmu_domain->cd);
if (ret)
goto out_unlock;
@@ -689,6 +689,7 @@ struct arm_smmu_master {
struct list_head domain_head;
struct arm_smmu_stream *streams;
struct arm_smmu_s1_cfg s1_cfg;
+ bool has_stage1;
struct arm_smmu_s2_cfg *s2_cfg;
unsigned int num_streams;
bool ats_enabled;