diff mbox series

[v2,3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs

Message ID 20230509182504.2997252-4-evan@rivosinc.com
State New
Headers
Series RISC-V: Export Zba, Zbb to usermode via hwprobe |

Commit Message

Evan Green May 9, 2023, 6:25 p.m. UTC 
  Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
These are accurately reported per CPU.

Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

---

Changes in v2:
 - Fixed typo s/supporte/supported/ (Conor)
 - Fixed copypasta s/IMA_ZBB/EXT_ZBB/ (Conor)
 - Added Zbs

 Documentation/riscv/hwprobe.rst       | 10 ++++++
 arch/riscv/include/uapi/asm/hwprobe.h |  3 ++
 arch/riscv/kernel/sys_riscv.c         | 48 +++++++++++++++++++++++----
 3 files changed, 54 insertions(+), 7 deletions(-)

Comments

Conor Dooley May 9, 2023, 6:33 p.m. UTC | #1 
On Tue, May 09, 2023 at 11:25:03AM -0700, Evan Green wrote:
> +		if (riscv_isa_extension_available(isainfo->isa, ZBA))
> +			pair->value |= RISCV_HWPROBE_EXT_ZBA;
> +		else
> +			missing |= RISCV_HWPROBE_EXT_ZBA;

Part of me wonders if we should just have a macro for this, since it's
just boilerplate w/ the only "variable" being the extension name.

Just a thought, and we'll have plenty more cracks at changing things
here, so:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.
Heiko Stübner May 10, 2023, 2:47 p.m. UTC | #2 
Am Dienstag, 9. Mai 2023, 20:25:03 CEST schrieb Evan Green:
> Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
> These are accurately reported per CPU.
> 
> Signed-off-by: Evan Green <evan@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>

though a part of me wonders, what happened to Zbc ;-)
Palmer Dabbelt June 19, 2023, 11:55 p.m. UTC | #3 
On Wed, 10 May 2023 07:47:54 PDT (-0700), heiko@sntech.de wrote:
> Am Dienstag, 9. Mai 2023, 20:25:03 CEST schrieb Evan Green:
>> Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
>> These are accurately reported per CPU.
>>
>> Signed-off-by: Evan Green <evan@rivosinc.com>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>

This one too.

> though a part of me wonders, what happened to Zbc ;-)

I think we all just keep forgetting about it as this round of HW has 
missed out on it.  If you care enough to send a patch I'm happy to pick 
it up ;)
diff mbox series

Patch

diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index 9f0dd62dcb5d..fb25670ef0e5 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -64,6 +64,16 @@  The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
     by version 2.2 of the RISC-V ISA manual.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
+       supported, as defined in version 1.0 of the Bit-Manipulation ISA
+       extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
+       in version 1.0 of the Bit-Manipulation ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
+       in version 1.0 of the Bit-Manipulation ISA extensions.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 8d745a4ad8a2..853f8f6d9a42 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -25,6 +25,9 @@  struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_IMA_EXT_0	4
 #define		RISCV_HWPROBE_IMA_FD		(1 << 0)
 #define		RISCV_HWPROBE_IMA_C		(1 << 1)
+#define		RISCV_HWPROBE_EXT_ZBA		(1 << 2)
+#define		RISCV_HWPROBE_EXT_ZBB		(1 << 3)
+#define		RISCV_HWPROBE_EXT_ZBS		(1 << 4)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 5db29683ebee..fe655db19ab4 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -121,6 +121,46 @@  static void hwprobe_arch_id(struct riscv_hwprobe *pair,
 	pair->value = id;
 }
 
+static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
+			     const struct cpumask *cpus)
+{
+	int cpu;
+	u64 missing = 0;
+
+	pair->value = 0;
+	if (has_fpu())
+		pair->value |= RISCV_HWPROBE_IMA_FD;
+
+	if (riscv_isa_extension_available(NULL, c))
+		pair->value |= RISCV_HWPROBE_IMA_C;
+
+	/*
+	 * Loop through and record extensions that 1) anyone has, and 2) anyone
+	 * doesn't have.
+	 */
+	for_each_cpu(cpu, cpus) {
+		struct riscv_isainfo *isainfo = &hart_isa[cpu];
+
+		if (riscv_isa_extension_available(isainfo->isa, ZBA))
+			pair->value |= RISCV_HWPROBE_EXT_ZBA;
+		else
+			missing |= RISCV_HWPROBE_EXT_ZBA;
+
+		if (riscv_isa_extension_available(isainfo->isa, ZBB))
+			pair->value |= RISCV_HWPROBE_EXT_ZBB;
+		else
+			missing |= RISCV_HWPROBE_EXT_ZBB;
+
+		if (riscv_isa_extension_available(isainfo->isa, ZBS))
+			pair->value |= RISCV_HWPROBE_EXT_ZBS;
+		else
+			missing |= RISCV_HWPROBE_EXT_ZBS;
+	}
+
+	/* Now turn off reporting features if any CPU is missing it. */
+	pair->value &= ~missing;
+}
+
 static u64 hwprobe_misaligned(const struct cpumask *cpus)
 {
 	int cpu;
@@ -164,13 +204,7 @@  static void hwprobe_one_pair(struct riscv_hwprobe *pair,
 		break;
 
 	case RISCV_HWPROBE_KEY_IMA_EXT_0:
-		pair->value = 0;
-		if (has_fpu())
-			pair->value |= RISCV_HWPROBE_IMA_FD;
-
-		if (riscv_isa_extension_available(NULL, c))
-			pair->value |= RISCV_HWPROBE_IMA_C;
-
+		hwprobe_isa_ext0(pair, cpus);
 		break;
 
 	case RISCV_HWPROBE_KEY_CPUPERF_0: