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Tue, 9 May 2023 06:17:34 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 4/5] iommu/amd: Do not Invalidate IRT when disable IRTE caching Date: Tue, 9 May 2023 07:16:45 -0400 Message-ID: <20230509111646.369661-5-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230509111646.369661-1-suravee.suthikulpanit@amd.com> References: <20230509111646.369661-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT004:EE_|SA3PR12MB7832:EE_ X-MS-Office365-Filtering-Correlation-Id: a518cd2f-6fc1-422c-d293-08db507efdd8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: V11yhg3vLvuAznKL4fqVe1v3p2vdg8PJy/8HFpUY6i5ab2oDrIAC7E8h8R/Yxd2ARA4DZvZUzxgo3g+yeLO3DdhYTDJJ3BKSU7cVlM/7xbVroXU/Npm417cF3m9FSH8bbDsyex/qGSlwQl78UEe8SLmdOt6EzsC38PM5Epyk259lR3VYBN7CWowY4uOX7V6b9xiDxk506LS4k/UFeVPQ/Qiu7TWLN65/kcCO3WB0pbzh+chCPg2M0AEutpMHReIdPfb4R0sEo8szcEBdNRBUSUZAXRrHaDINLdJlENjU6GkCs3N5W8Ei64kf/RCdVwtQqXN+0a1+HJYpapV994j78notBfS0ZHiY5pNo4nujKakpZkyVRIMqMkiUIvZMgcSg6xDLDmbq45ODoFLjo1LQ7FQVm9lsNqWx94k1YORPMlTnxyydXv7g7Zyu/IX8upMM7oT8bSXiagDFtgsVAzl4WxmJTwImh3g78ILO7zZy75CA2d2wc8JN2AxCeMbVNo5egeAId+IMd7lLJTDz2E44qZtbAVBNub0noKniLVgUMkW8vxdJT8uXVtOhcTGntUjm3zaMREZadEM02OHY6XHHAkzpsIZPx2nAs14xDnzP1PRYuiuBLeHSTcAUFFt6tSJd0kAmMZNPUyAh+MiRtAytx0WFLifyuKB4tNLmmFa8ky5mN5tcLMihy4OhrjjU/qlCK5WyUYSpl/s8g1DzG9DYzCIxo6t5J+Wkf57vQMuKbgrdBb8OaQD3guRnNljRtJqRuYrJDqyURqiTZ3kMsfrDXw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(396003)(39860400002)(136003)(451199021)(36840700001)(46966006)(40470700004)(2616005)(40460700003)(6666004)(26005)(1076003)(8676002)(8936002)(7696005)(86362001)(82310400005)(44832011)(478600001)(16526019)(36756003)(40480700001)(186003)(2906002)(5660300002)(356005)(47076005)(36860700001)(54906003)(83380400001)(81166007)(316002)(70586007)(4326008)(70206006)(41300700001)(110136005)(426003)(336012)(82740400003)(36900700001);DIR:OUT;SFP:1101; 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Therefore, add logic to bypass the operation. Suggested-by: Joao Martins Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 0c4a2796bb0a..51c2b018433d 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1273,12 +1273,24 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) u32 devid; u16 last_bdf = iommu->pci_seg->last_bdf; + if (iommu->irtcachedis_enabled) + return; + for (devid = 0; devid <= last_bdf; devid++) iommu_flush_irt(iommu, devid); iommu_completion_wait(iommu); } +static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid) +{ + if (iommu->irtcachedis_enabled) + return; + + iommu_flush_irt(iommu, devid); + iommu_completion_wait(iommu); +} + void iommu_flush_all_caches(struct amd_iommu *iommu) { if (iommu_feature(iommu, FEATURE_IA)) { @@ -3028,8 +3040,7 @@ static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); return 0; } @@ -3048,8 +3059,7 @@ static int modify_irte(struct amd_iommu *iommu, table->table[index] = irte->val; raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); return 0; } @@ -3067,8 +3077,7 @@ static void free_irte(struct amd_iommu *iommu, u16 devid, int index) iommu->irte_ops->clear_allocated(table, index); raw_spin_unlock_irqrestore(&table->lock, flags); - iommu_flush_irt(iommu, devid); - iommu_completion_wait(iommu); + iommu_flush_irt_and_complete(iommu, devid); } static void irte_prepare(void *entry,