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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d12-20020a63360c000000b0052cbf501db2si1126236pga.68.2023.05.09.01.37.13; Tue, 09 May 2023 01:37:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=SC2w1S+a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233827AbjEIIXW (ORCPT + 99 others); Tue, 9 May 2023 04:23:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234852AbjEIIXK (ORCPT ); Tue, 9 May 2023 04:23:10 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC5CDD87C for ; Tue, 9 May 2023 01:23:04 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-ba2526a8918so5459744276.1 for ; Tue, 09 May 2023 01:23:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683620584; x=1686212584; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=dcm1xpxsxE4LsssubrxTulCcSjnntMYzhlXL+xNXQmE=; b=SC2w1S+a9UIFvlzG/TtznNrQM+SlztRpmqJCYhUvVl3bP2kqiZJcBIq0kELz0fcd6F lpHQOcplW4pxPwsm08WZ+PusejT5ou5sP7zuDP6CZ34i4FJePoNuzvqzn5sjkToZew9g yyXZmWogXOtCvOn336dxqH7oVGlk3eNt3udoThPp+93HOv+EaQIl7EBnaPGhewnQO2gW omPB3iQ/g8cmfJuDdSe2MpCVPFZtt8ymh1Q0eg9jntvPRvczEmU+Q+u0nolSgnCBEqT4 MI7PpWyia0BQe7RjZ9VisNlwJgDjIVk3l+6OTlwWB9phoNHq7gW4mTmEhsztDcRXvcJM saTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683620584; x=1686212584; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=dcm1xpxsxE4LsssubrxTulCcSjnntMYzhlXL+xNXQmE=; b=CtoqYBSwazQ0UVg9+Vr4qd4f0DwbnvkSEQX+isIs5WljTZK86vpK5crwIChvQgcTum fjD4gGNKQp75r6cKUXLSqYZiZZKeKk8eCg0wW4yvTdH7iXunUKSYLSR0iKeAgmEVRBAE Pef+yItAhx3HOClq6b8jdUq6z25LXqbQ4qooxSQgY7k+AhMLDjAVWCm9k0gPB/IZDWof fIguEKw75F2vttl4ncUGFS2UBIfOn/XYL777fUCmk10/bTb9LTnNPIbiK4WGFYNXIdb8 DWQTAWZbC953cJ4DMpWqIe+gprKLzR87k8ff7muYZ8Xjxg/EK2JK4qDgqdzfponKxmn6 Fxcw== X-Gm-Message-State: AC+VfDziBMaQEbMm33itS8m9X5dIgqVi8ZGdWl9/QtcaJMoMTKIlRlEt HdoccNhSizlSJQb+kl3OS4yZ7dV7sNlf7Q== X-Received: from joychakr.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:6ea]) (user=joychakr job=sendgmr) by 2002:a5b:ed1:0:b0:b9a:6508:1b5f with SMTP id a17-20020a5b0ed1000000b00b9a65081b5fmr5769008ybs.11.1683620584172; Tue, 09 May 2023 01:23:04 -0700 (PDT) Date: Tue, 9 May 2023 08:22:42 +0000 In-Reply-To: <20230509082244.1069623-1-joychakr@google.com> Mime-Version: 1.0 References: <20230509082244.1069623-1-joychakr@google.com> X-Mailer: git-send-email 2.40.1.521.gf1e218fcd8-goog Message-ID: <20230509082244.1069623-4-joychakr@google.com> Subject: [PATCH v10 3/5] spi: dw: Add DMA directional capability check From: Joy Chakraborty To: Serge Semin , Mark Brown , Andy Shevchenko Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, manugautam@google.com, rohitner@google.com, Joy Chakraborty X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765405048317488855?= X-GMAIL-MSGID: =?utf-8?q?1765405048317488855?= Check capabilities of DMA controller during init to make sure it is capable of handling MEM2DEV for tx channel, DEV2MEM for rx channel. Current DW DMA driver requires both tx and rx channel to be configured and functional for any kind of transfers to take effect including half duplex. Hence, check for both tx and rx direction and fail on unavailbility of either. Signed-off-by: Joy Chakraborty Reviewed-by: Serge Semin Tested-by: Serge Semin * tested on Baikal-T1 based system with DW SPI-looped back interface transferring a chunk of data with DFS:8,12,16. --- drivers/spi/spi-dw-dma.c | 41 +++++++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c index f19c092920a1..2363317a0dca 100644 --- a/drivers/spi/spi-dw-dma.c +++ b/drivers/spi/spi-dw-dma.c @@ -72,12 +72,22 @@ static void dw_spi_dma_maxburst_init(struct dw_spi *dws) dw_writel(dws, DW_SPI_DMATDLR, dws->txburst); } -static void dw_spi_dma_sg_burst_init(struct dw_spi *dws) +static int dw_spi_dma_caps_init(struct dw_spi *dws) { - struct dma_slave_caps tx = {0}, rx = {0}; + struct dma_slave_caps tx, rx; + int ret; + + ret = dma_get_slave_caps(dws->txchan, &tx); + if (ret) + return ret; - dma_get_slave_caps(dws->txchan, &tx); - dma_get_slave_caps(dws->rxchan, &rx); + ret = dma_get_slave_caps(dws->rxchan, &rx); + if (ret) + return ret; + + if (!(tx.directions & BIT(DMA_MEM_TO_DEV) && + rx.directions & BIT(DMA_DEV_TO_MEM))) + return -ENXIO; if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0) dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst); @@ -87,6 +97,8 @@ static void dw_spi_dma_sg_burst_init(struct dw_spi *dws) dws->dma_sg_burst = rx.max_sg_burst; else dws->dma_sg_burst = 0; + + return 0; } static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) @@ -95,6 +107,7 @@ static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx; struct pci_dev *dma_dev; dma_cap_mask_t mask; + int ret = -EBUSY; /* * Get pci device for DMA controller, currently it could only @@ -124,20 +137,25 @@ static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) init_completion(&dws->dma_completion); - dw_spi_dma_maxburst_init(dws); + ret = dw_spi_dma_caps_init(dws); + if (ret) + goto free_txchan; - dw_spi_dma_sg_burst_init(dws); + dw_spi_dma_maxburst_init(dws); pci_dev_put(dma_dev); return 0; +free_txchan: + dma_release_channel(dws->txchan); + dws->txchan = NULL; free_rxchan: dma_release_channel(dws->rxchan); dws->rxchan = NULL; err_exit: pci_dev_put(dma_dev); - return -EBUSY; + return ret; } static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws) @@ -163,12 +181,17 @@ static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws) init_completion(&dws->dma_completion); - dw_spi_dma_maxburst_init(dws); + ret = dw_spi_dma_caps_init(dws); + if (ret) + goto free_txchan; - dw_spi_dma_sg_burst_init(dws); + dw_spi_dma_maxburst_init(dws); return 0; +free_txchan: + dma_release_channel(dws->txchan); + dws->txchan = NULL; free_rxchan: dma_release_channel(dws->rxchan); dws->rxchan = NULL;