diff mbox series

[v2,3/3] arm64: dts: ti: k3-j7200-mcu-wakeup: Update fss node and hbmc_mux

Message ID 20230505115858.7391-4-vaishnav.a@ti.com
State New
Headers
Series arm64: dts: ti: k3-j7200: Fixes for various dtbs_checks warnings |

Commit Message

Vaishnav Achath May 5, 2023, 11:58 a.m. UTC 
  From: Nishanth Menon <nm@ti.com>

fss node claims to be a syscon node, while it actually is a simple bus
where ospi, hbmc peripherals are located and a mux for path select
between OSPI and Hyperbus which can be modelled as a reg-mux. So model
it accordingly and use reg-mux to describe the hbmc-mux. Also update
the region size to the correct values as per the TRM.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---

V1->V2:
 * Address feedback from Udit to limit the FSS register region size as
 per TRM.
 * Use reg-mux changes to simplify the hbmc-mux modelling.
 * Update commit message to reflect changes.

Depends on:
 https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/

 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

Comments

Vignesh Raghavendra May 9, 2023, 10:41 a.m. UTC | #1 
On 05/05/23 17:28, Vaishnav Achath wrote:
> From: Nishanth Menon <nm@ti.com>
> 
> fss node claims to be a syscon node, while it actually is a simple bus

FSS

> where ospi, hbmc peripherals are located and a mux for path select

OSPI, HBMC

> between OSPI and Hyperbus which can be modelled as a reg-mux. So model
> it accordingly and use reg-mux to describe the hbmc-mux. Also update
> the region size to the correct values as per the TRM.
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
> ---
> 
> V1->V2:
>  * Address feedback from Udit to limit the FSS register region size as
>  per TRM.
>  * Use reg-mux changes to simplify the hbmc-mux modelling.
>  * Update commit message to reflect changes.
> 
> Depends on:
>  https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/
> 
>  arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index b58a31371bf3..333564ca9c91 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -338,22 +338,23 @@
>  		status = "disabled";
>  	};
>  
> -	fss: syscon@47000000 {
> -		compatible = "syscon", "simple-mfd";
> -		reg = <0x00 0x47000000 0x00 0x100>;
> +	fss: bus@47000000 {
> +		compatible = "simple-bus";
> +		reg = <0x00 0x47000000 0x0 0x7c>;

                                       ^^^^ 0x00

I know the registers only go up to 0x7c, but its convention to map
entire region that is reserved for the IP irrespective of how many
registers are actually valid (I see this across arm64 SoC Vendors).
Eg as per TRM,  Table 203 MCU Domain map:

MCU_FSS0_CFG 0x0047000000 - 0x00470000FF (256B)




>  		#address-cells = <2>;
>  		#size-cells = <2>;
>  		ranges;
>  
> -		hbmc_mux: hbmc-mux {
> -			compatible = "mmio-mux";
> +		hbmc_mux: mux-controller@47000004 {
> +			compatible = "reg-mux";
> +			reg = <0x00 0x47000004 0x00 0x2>;
>  			#mux-control-cells = <1>;
>  			mux-reg-masks = <0x4 0x2>; /* HBMC select */
>  		};
>  
>  		hbmc: hyperbus@47034000 {
>  			compatible = "ti,am654-hbmc";
> -			reg = <0x00 0x47034000 0x00 0x100>,
> +			reg = <0x00 0x47034000 0x00 0x0c>,

Hmm, doesn't look correct? I see register addresses up to 0x47034048h in
TRM?

I prefer to map entire region reserved in the SoC memory map:
MCU_FSS0_HPB_CTRL 0x0047034000 - 0x00470340FF (256B)


>  				<0x05 0x00000000 0x01 0x0000000>;
>  			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
>  			clocks = <&k3_clks 102 0>;
Andrew Davis May 10, 2023, 3:30 p.m. UTC | #2 
On 5/9/23 5:41 AM, Vignesh Raghavendra wrote:
> 
> 
> On 05/05/23 17:28, Vaishnav Achath wrote:
>> From: Nishanth Menon <nm@ti.com>
>>
>> fss node claims to be a syscon node, while it actually is a simple bus
> 
> FSS
> 
>> where ospi, hbmc peripherals are located and a mux for path select
> 
> OSPI, HBMC
> 
>> between OSPI and Hyperbus which can be modelled as a reg-mux. So model
>> it accordingly and use reg-mux to describe the hbmc-mux. Also update
>> the region size to the correct values as per the TRM.
>>
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
>> ---
>>
>> V1->V2:
>>   * Address feedback from Udit to limit the FSS register region size as
>>   per TRM.
>>   * Use reg-mux changes to simplify the hbmc-mux modelling.
>>   * Update commit message to reflect changes.
>>
>> Depends on:
>>   https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/
>>
>>   arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 13 +++++++------
>>   1 file changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
>> index b58a31371bf3..333564ca9c91 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
>> @@ -338,22 +338,23 @@
>>   		status = "disabled";
>>   	};
>>   
>> -	fss: syscon@47000000 {
>> -		compatible = "syscon", "simple-mfd";
>> -		reg = <0x00 0x47000000 0x00 0x100>;
>> +	fss: bus@47000000 {
>> +		compatible = "simple-bus";
>> +		reg = <0x00 0x47000000 0x0 0x7c>;
> 
>                                         ^^^^ 0x00
> 
> I know the registers only go up to 0x7c, but its convention to map
> entire region that is reserved for the IP irrespective of how many
> registers are actually valid (I see this across arm64 SoC Vendors).
> Eg as per TRM,  Table 203 MCU Domain map:
> 
> MCU_FSS0_CFG 0x0047000000 - 0x00470000FF (256B)
> 
> 
> 
> 
>>   		#address-cells = <2>;
>>   		#size-cells = <2>;
>>   		ranges;
>>   
>> -		hbmc_mux: hbmc-mux {
>> -			compatible = "mmio-mux";
>> +		hbmc_mux: mux-controller@47000004 {
>> +			compatible = "reg-mux";
>> +			reg = <0x00 0x47000004 0x00 0x2>;
>>   			#mux-control-cells = <1>;
>>   			mux-reg-masks = <0x4 0x2>; /* HBMC select */
>>   		};
>>   
>>   		hbmc: hyperbus@47034000 {
>>   			compatible = "ti,am654-hbmc";
>> -			reg = <0x00 0x47034000 0x00 0x100>,
>> +			reg = <0x00 0x47034000 0x00 0x0c>,
> 
> Hmm, doesn't look correct? I see register addresses up to 0x47034048h in
> TRM?
> 
> I prefer to map entire region reserved in the SoC memory map:
> MCU_FSS0_HPB_CTRL 0x0047034000 - 0x00470340FF (256B)
> 

I do agree here 0x100 is more clean, but we do have to watch for the
holes we have in memory right after some register spaces which cause
SErrors on access..

Either way this reg change should have been its own patch, not squashed
into this otherwise correct s/mmio-mux/reg-mux patch.

Andrew

> 
>>   				<0x05 0x00000000 0x01 0x0000000>;
>>   			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
>>   			clocks = <&k3_clks 102 0>;
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index b58a31371bf3..333564ca9c91 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -338,22 +338,23 @@ 
 		status = "disabled";
 	};
 
-	fss: syscon@47000000 {
-		compatible = "syscon", "simple-mfd";
-		reg = <0x00 0x47000000 0x00 0x100>;
+	fss: bus@47000000 {
+		compatible = "simple-bus";
+		reg = <0x00 0x47000000 0x0 0x7c>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
 
-		hbmc_mux: hbmc-mux {
-			compatible = "mmio-mux";
+		hbmc_mux: mux-controller@47000004 {
+			compatible = "reg-mux";
+			reg = <0x00 0x47000004 0x00 0x2>;
 			#mux-control-cells = <1>;
 			mux-reg-masks = <0x4 0x2>; /* HBMC select */
 		};
 
 		hbmc: hyperbus@47034000 {
 			compatible = "ti,am654-hbmc";
-			reg = <0x00 0x47034000 0x00 0x100>,
+			reg = <0x00 0x47034000 0x00 0x0c>,
 				<0x05 0x00000000 0x01 0x0000000>;
 			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 			clocks = <&k3_clks 102 0>;