From patchwork Thu May 4 03:37:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 89907 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp35219vqo; Wed, 3 May 2023 20:54:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5A0MJGOPA4QBDE/+RoyAw1kqt2lPgSsYNTE/o0rEl6y+uFDzCu/S2YutS9khdsUl3x2Cu+ X-Received: by 2002:a17:90a:e008:b0:24e:1177:f467 with SMTP id u8-20020a17090ae00800b0024e1177f467mr931789pjy.12.1683172497428; Wed, 03 May 2023 20:54:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683172497; cv=none; d=google.com; s=arc-20160816; b=Z9VrHfgtAxmECBqNgWKEe9zNeeuDpEqiZBHxjFKQDPX0vBSY7i7MN6KcP9z4oi2l0R OD2c/ABOvZaDJhKicpjD5242wJzv+GZ6qKASTUmxGerKZ5goSwsqhD8AEyd7hkNIMWzg reK3lJBl9GrHLrbuD4cj9l6lqB0QRAHuA+hvTzzjXeOHwoCDYzk0VkzvDDebaQShDQ+y BeIn8b2OnmdWMk4UadTCbB/vscWXtEcqJMXMcgwUfPhbqj7/0jzs0WweY0LNk2I2joZo 4cT7ZSbao94APr7hGLsMwpAEbUMPHbr9Bsi5E2ToqJ+1QDBsKiXNSkccpUwXVc9PcpIx xZ+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fmC5zm44vt8pLpbtXMcwI8CDqLllNVPAuPsDC/gMEeo=; b=SjhZjpPQXZy2Vdaw4bUlZI8MbN7q3QIn4kdkUpXcuSsBaVMFFXvWHNOZBAkyFcUiLt +IbS4gMLcjre19qYnQ3QXPDWltuEMbIPE7bR8LstN2/r34HQwCLBULHWWQ0yLor6XsNZ 9HYRaIQ3Sfjj2GPlQqJ/pPkdYXiD314DtYUNnJDHpkzwplwDgtHzcX6oVsswKiZfOwm9 kwArtxqzaYQIq+TWBQ/xxpSGm1vls6c1N22TmSaNqqowaRIymuz7gISQE7Ne6JjDYjaq x0FyacGfLd1R2r7VMu+N8CadH61EsZ/h89HV3c679d8gCKSzALswPBCRAUccUqj4zP8N wWxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=g1zCDscF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w24-20020a17090aea1800b0024de4be9639si11038778pjy.34.2023.05.03.20.54.40; Wed, 03 May 2023 20:54:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=g1zCDscF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230010AbjEDDjB (ORCPT + 99 others); Wed, 3 May 2023 23:39:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229944AbjEDDi3 (ORCPT ); Wed, 3 May 2023 23:38:29 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 350841FCB; Wed, 3 May 2023 20:37:57 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1aaed87d8bdso35496855ad.3; Wed, 03 May 2023 20:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683171477; x=1685763477; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fmC5zm44vt8pLpbtXMcwI8CDqLllNVPAuPsDC/gMEeo=; b=g1zCDscFI5KMK9NH8K2vC67OF6clzG+Fbj6cg2q3EhBNrrTH66t6n5R8iKn9YG3eyb 5jnMUYLmWQsOZoCUWMef5nZ4XCZ8VQ/X9a1Fx9uXlNz7zc5cGjr5wb1jZTd2zrL0yjHI JN8HjRLaQSdxpZAH+jgA2FvNFmkcXZZTmQSSebY047L2gTVFqFQ/OP37gm0ZJQGZ5K2p 4Gl4iWyp8u94/aG1XPFWxExpMYw1QAd0QJcbQptvY0MDz+xvuV7zux4Md/5QA7XSULyE UFp32J8PWceo6m3FzygPFhs6rQuseGVoF0NsiNf/scMwsBc4dzvWyu2HC76U8cAxOVUr G8SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683171477; x=1685763477; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fmC5zm44vt8pLpbtXMcwI8CDqLllNVPAuPsDC/gMEeo=; b=hyLI2UxHuHrOEW/5x+gD7b1xd5kaXSGyYUOSppcCgIeTfVlKUJLxCmCgzT7h/EFbog P/PfTweMkOlPXDCTiq9EXv0phC7M4CzobmmY7N1/dgW7Qd97tCqvUOFLlYuIHLhibEdC 1iXApgw268b33rMZrSizk6q95Uq4znTAZlRy1lvYVZ746i+gFaM60/eBgShEwptAbUjd 2AGk9lNuzeJ3JJaDGE85+MPeuIGE7uOeCb0xUqbPnHQ+TJUn20Lr2m5d5g3PnP/HAY/u 4wN7jeT+ZWLmTSW+62safdWet5SQuNbEO7Tr2FnPB1Mben4Wx0wBiVqQq8oiiFE3IuTC GH9g== X-Gm-Message-State: AC+VfDxnChA86IFwhg8kdiWoHCRDz/JOU8qGae9Y/6+OLoJ+5+ugDwDS xT9m6JbscgEu9EXwPMEYjgI= X-Received: by 2002:a17:902:e748:b0:1a6:961e:fcfe with SMTP id p8-20020a170902e74800b001a6961efcfemr2909690plf.30.1683171476857; Wed, 03 May 2023 20:37:56 -0700 (PDT) Received: from a28aa0606c51.. (60-250-192-107.hinet-ip.hinet.net. [60.250.192.107]) by smtp.gmail.com with ESMTPSA id jj3-20020a170903048300b001ab849b46d3sm468761plb.178.2023.05.03.20.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 20:37:56 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org, tmaimon77@gmail.com, catalin.marinas@arm.com, will@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v9 07/10] arm64: dts: nuvoton: Add initial ma35d1 device tree Date: Thu, 4 May 2023 03:37:23 +0000 Message-Id: <20230504033726.93-8-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230504033726.93-1-ychuang570808@gmail.com> References: <20230504033726.93-1-ychuang570808@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764934284733969248?= X-GMAIL-MSGID: =?utf-8?q?1764934284733969248?= From: Jacky Huang Add initial device tree support for Nuvoton ma35d1 SoC, including cpu, clock, reset, and serial controllers. Add reference boards som-256m and iot-512m. Signed-off-by: Jacky Huang Acked-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/nuvoton/Makefile | 2 + .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 56 +++++ .../boot/dts/nuvoton/ma35d1-som-256m.dts | 56 +++++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 232 ++++++++++++++++++ 4 files changed, 346 insertions(+) create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile index a99dab90472a..c11ab4eac9c7 100644 --- a/arch/arm64/boot/dts/nuvoton/Makefile +++ b/arch/arm64/boot/dts/nuvoton/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-iot-512m.dtb +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-som-256m.dtb diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts new file mode 100644 index 000000000000..b89e2be6abae --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-IoT"; + compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */ + }; + + clk_hxt: clock-hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&clk { + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = "integer", + "fractional", + "integer", + "integer", + "integer"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts new file mode 100644 index 000000000000..a1ebddecb7f8 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-SOM"; + compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */ + }; + + clk_hxt: clock-hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&clk { + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = "integer", + "fractional", + "integer", + "integer", + "integer"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi new file mode 100644 index 000000000000..1f1139082cb7 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "nuvoton,ma35d1"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@50801000 { + compatible = "arm,gic-400"; + reg = <0x0 0x50801000 0 0x1000>, /* GICD */ + <0x0 0x50802000 0 0x2000>, /* GICC */ + <0x0 0x50804000 0 0x2000>, /* GICH */ + <0x0 0x50806000 0 0x2000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + interrupt-parent = <&gic>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sys: system-management@40460000 { + compatible = "nuvoton,ma35d1-reset"; + reg = <0x0 0x40460000 0x0 0x200>; + #reset-cells = <1>; + }; + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk"; + reg = <0x00000000 0x40460200 0x0 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + }; + + uart0: serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40700000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + status = "disabled"; + }; + + uart1: serial@40710000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40710000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART1_GATE>; + status = "disabled"; + }; + + uart2: serial@40720000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40720000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART2_GATE>; + status = "disabled"; + }; + + uart3: serial@40730000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40730000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART3_GATE>; + status = "disabled"; + }; + + uart4: serial@40740000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40740000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART4_GATE>; + status = "disabled"; + }; + + uart5: serial@40750000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40750000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART5_GATE>; + status = "disabled"; + }; + + uart6: serial@40760000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40760000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART6_GATE>; + status = "disabled"; + }; + + uart7: serial@40770000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40770000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART7_GATE>; + status = "disabled"; + }; + + uart8: serial@40780000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40780000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART8_GATE>; + status = "disabled"; + }; + + uart9: serial@40790000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40790000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART9_GATE>; + status = "disabled"; + }; + + uart10: serial@407a0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407a0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART10_GATE>; + status = "disabled"; + }; + + uart11: serial@407b0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407b0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART11_GATE>; + status = "disabled"; + }; + + uart12: serial@407c0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407c0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART12_GATE>; + status = "disabled"; + }; + + uart13: serial@407d0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407d0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART13_GATE>; + status = "disabled"; + }; + + uart14: serial@407e0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407e0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART14_GATE>; + status = "disabled"; + }; + + uart15: serial@407f0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407f0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART15_GATE>; + status = "disabled"; + }; + + uart16: serial@40880000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40880000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART16_GATE>; + status = "disabled"; + }; + }; +};