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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j191-20020a6380c8000000b00524d36c533dsi17591445pgd.98.2023.04.27.06.10.35; Thu, 27 Apr 2023 06:11:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20221208 header.b=3DLTZ423; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243797AbjD0Mdw (ORCPT + 99 others); Thu, 27 Apr 2023 08:33:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243851AbjD0Mdq (ORCPT ); Thu, 27 Apr 2023 08:33:46 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B3BC5BAD for ; Thu, 27 Apr 2023 05:33:40 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b8f32cc8c31so14480233276.2 for ; Thu, 27 Apr 2023 05:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682598819; x=1685190819; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=fLvnCO6evlKbK+xj/d2Id6gaw49UQ3nh6G31gbqAkCk=; b=3DLTZ423zj75HZE3dLX2ol2fkvJhx+OfxNx9TMkA1hLwBabuiMsxVL4wEmuUfF45UQ +i0GLG+Em2uXwmyHcJLuJRz+vWS5vYw+EdRJvVSn8prLzEyev1YSa/j+nCoeGTno7mIi 56DwSlzeCplHTll72n8yKAasRvyfeO6rsIFX5krBUDP7yXf9nWgwyHjFnGAR7KN3XITs ggptjW7770nyYfIoSP2/MyjD9plolbqIVxbccmGTDnK3ijXt0EvYQzVSbjIXOrCmvRyb SThdIXn6S3njt7z3q77aTsYuoeW9Bbf8L+UTaIWZAOdV+J1f4sLYODoPz9ZCNsw1QcgN 7UJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682598819; x=1685190819; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=fLvnCO6evlKbK+xj/d2Id6gaw49UQ3nh6G31gbqAkCk=; b=j67E6NB1gugK4sJN8b+uioFrzantLKMWXF4dDiO1nvX7GoUSa4Kv3KimzutpL8SF0w KjYBlmZ+c3825vi/GpzWENMrh1VkrzjJwyyr5NeqMX/lkub3iclig1wkRbwKtIghwn+J bgLUa/lqarSPPW6NvgQrMSYd2bZpO2lwzaP7wQ2ft8cSxXnzgkt9DEBbGK6Y91M4l19k +wzsCcMz+regdgkSc277NgQUfQWLZW0oYbrobty7YXwh3L/bSoXizsHhGqouTss8L9We XQDP0sBFI6THlImaBX4SLSXuDwgCWBpPxC5zWHg42hVCaLkwa/HL7RTT4GHCFGd2y1gT I7dg== X-Gm-Message-State: AC+VfDy2RLIJ+ey2Yx+1D39mzZzstYJLDis/5wspwTOzH0Big5YblsDI rVo+pugGkrsnWUKtSOzC1Im3WXISaRVjyg== X-Received: from joychakr.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:6ea]) (user=joychakr job=sendgmr) by 2002:a25:5843:0:b0:b99:df0b:cb1e with SMTP id m64-20020a255843000000b00b99df0bcb1emr501204ybb.4.1682598819554; Thu, 27 Apr 2023 05:33:39 -0700 (PDT) Date: Thu, 27 Apr 2023 12:33:13 +0000 In-Reply-To: <20230427123314.1997152-1-joychakr@google.com> Mime-Version: 1.0 References: <20230427123314.1997152-1-joychakr@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Message-ID: <20230427123314.1997152-5-joychakr@google.com> Subject: [PATCH v9 4/5] spi: dw: Add DMA address widths capability check From: Joy Chakraborty To: Serge Semin , Mark Brown , Andy Shevchenko Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, manugautam@google.com, rohitner@google.com, Joy Chakraborty X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764335104943572325?= X-GMAIL-MSGID: =?utf-8?q?1764335104943572325?= Store address width capabilities of DMA controller during init and check the same per transfer to make sure the bits/word requirement can be met. Current DW DMA driver requires both tx and rx channel to be configured and functional hence a subset of both tx and rx channel address width capability is checked with the width requirement(n_bytes) for a transfer. Signed-off-by: Joy Chakraborty Reviewed-by: Serge Semin Tested-by: Serge Semin * tested on Baikal-T1 based system with DW SPI-looped back interface transferring a chunk of data with DFS:8,12,16. --- drivers/spi/spi-dw-dma.c | 17 ++++++++++++++++- drivers/spi/spi-dw.h | 1 + 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c index 22d0727a3789..df819652901a 100644 --- a/drivers/spi/spi-dw-dma.c +++ b/drivers/spi/spi-dw-dma.c @@ -97,6 +97,15 @@ static int dw_spi_dma_caps_init(struct dw_spi *dws) dws->dma_sg_burst = rx.max_sg_burst; else dws->dma_sg_burst = 0; + + /* + * Assuming both channels belong to the same DMA controller hence the + * peripheral side address width capabilities most likely would be + * the same. + */ + dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths; + + return 0; } static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) @@ -237,8 +246,14 @@ static bool dw_spi_can_dma(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *xfer) { struct dw_spi *dws = spi_controller_get_devdata(master); + enum dma_slave_buswidth dma_bus_width; + + if (xfer->len <= dws->fifo_len) + return false; + + dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes); - return xfer->len > dws->fifo_len; + return dws->dma_addr_widths & BIT(dma_bus_width); } static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9e8eb2b52d5c..3962e6dcf880 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -190,6 +190,7 @@ struct dw_spi { struct dma_chan *rxchan; u32 rxburst; u32 dma_sg_burst; + u32 dma_addr_widths; unsigned long dma_chan_busy; dma_addr_t dma_addr; /* phy address of the Data register */ const struct dw_spi_dma_ops *dma_ops;