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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u82-20020a627955000000b0063b7862ed1csi16740548pfc.397.2023.04.26.03.45.55; Wed, 26 Apr 2023 03:46:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="JC7/vZBs"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240482AbjDZKdh (ORCPT + 99 others); Wed, 26 Apr 2023 06:33:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240415AbjDZKdL (ORCPT ); Wed, 26 Apr 2023 06:33:11 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B96E83C39; Wed, 26 Apr 2023 03:32:58 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33QAWjHe094342; Wed, 26 Apr 2023 05:32:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1682505165; bh=/fjVMPFor0N4zh6uT/1TO+jeMgeiyy8KcT62Sb/bxyo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JC7/vZBs6W/OEAAFs7aiTk7lZ1c5506txhJr4L5TFUK+uIRrwzVxnd5mkoqgdeNIp IPhIBxmo69QjgApxRAJ9gQ+eqZ2tteFfUdPHqyrk199Oq32io0NOLFzL1vkn5y4x2I PTgJPpKlZjG0Fo9U9LOFej1NIXRHaSgCkcmdQ674= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33QAWjUU112974 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 Apr 2023 05:32:45 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 26 Apr 2023 05:32:45 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 26 Apr 2023 05:32:45 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33QAWLRX036567; Wed, 26 Apr 2023 05:32:41 -0500 From: Udit Kumar To: , , , , , , , , , CC: Udit Kumar Subject: [PATCH 5/5] arm64: dts: ti: k3-j7200: Add bootph-pre-ram for u-boot Date: Wed, 26 Apr 2023 16:02:19 +0530 Message-ID: <20230426103219.1565266-6-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426103219.1565266-1-u-kumar1@ti.com> References: <20230426103219.1565266-1-u-kumar1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764235378261383056?= X-GMAIL-MSGID: =?utf-8?q?1764235378261383056?= Adding bootph-pre-ram property for pin mux needed by uboot. Signed-off-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 5 +++++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 2cdfd957dd12..1bcb94aec588 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -81,7 +81,9 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; &wkup_pmx0 { + bootph-pre-ram; mcu_uart0_pins_default: mcu_uart0_pins_default { + bootph-pre-ram; pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ @@ -91,6 +93,7 @@ J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ }; wkup_uart0_pins_default: wkup_uart0_pins_default { + bootph-pre-ram; pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ @@ -125,7 +128,9 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ }; &main_pmx0 { + bootph-pre-ram; main_uart0_pins_default: main_uart0_pins_default { + bootph-pre-ram; pinctrl-single,pins = < J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 269424154771..d2500837a0e8 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -119,7 +119,9 @@ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ }; &wkup_pmx2 { + bootph-pre-ram; wkup_i2c0_pins_default: wkup-i2c0-pins-default { + bootph-pre-ram; pinctrl-single,pins = < J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ @@ -129,6 +131,7 @@ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { + bootph-pre-ram; pinctrl-single,pins = < J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */