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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u17-20020a170903125100b001a6ce2cdb20si284568plh.244.2023.04.23.08.37.54; Sun, 23 Apr 2023 08:38:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=kV82mWIj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230250AbjDWOuD (ORCPT + 99 others); Sun, 23 Apr 2023 10:50:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230239AbjDWOt6 (ORCPT ); Sun, 23 Apr 2023 10:49:58 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F6F310E4 for ; Sun, 23 Apr 2023 07:49:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=6Ff9ArTJlhjOrz4Iyf2wgXUbGoNJsvmn8LGUWU50kvw=; b=kV82mWIjR+T/0TKTIHkNnso9y1 pj9TQUgP3KcKJTCLphT77F1zJ7XCv+tM2Ln5BULPV5hM/o+XqRkbY290rR5HQeg8QupGrJ5T9SOxp aNfGmJjQR/J3Pex79r/KaRVMGsMNh5jW2U+Kd5ui2gQ9VDDGyMqpKS0xmtlCpC6xaMAmdaggoZcLI mPZ4gVBBRNXQ7p72uO7m/mSBlsvcHHM4wDATqFzcQZc1Ax3Yi/fDQyNKfbFAQlcKPwvfLjhqNmneb yzAimWQG2DZaqeBAl0usp35JnkWNK2b7J1/wCocyiAlqss+4MLIuAvT9tLPKLZfICsRLbiC66PRjh GRpPLsLQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSI-00ANVs-Vu; Sun, 23 Apr 2023 16:12:43 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 14/40] drm/amd/display: add plane shaper LUT driver-private properties Date: Sun, 23 Apr 2023 13:10:26 -0100 Message-Id: <20230423141051.702990-15-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763981959560249434?= X-GMAIL-MSGID: =?utf-8?q?1763981959560249434?= Shaper 1D LUT delinearizes content before applying 3D LUT so that, it comes before 3D LUT. It's an optional property and drivers should attach it according to HW caps. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 ++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 19 +++++++++++++++++++ 4 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 8d4726978c6e..f41406ee96ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1332,6 +1332,20 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.plane_hdr_mult_property = prop; + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_SHAPER_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_lut_property = prop; + + prop = drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_SHAPER_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_lut_size_property = prop; + prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, "AMD_PLANE_LUT3D", 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 9d9dac26edfc..756d5f70be0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -391,6 +391,16 @@ struct amdgpu_mode_info { * @plane_hdr_mult_property: */ struct drm_property *plane_hdr_mult_property; + /** + * @shaper_lut_property: Plane property to set pre-blending shaper LUT + * that converts color content before 3D LUT. + */ + struct drm_property *plane_shaper_lut_property; + /** + * @shaper_lut_size_property: Plane property for the size of + * pre-blending shaper LUT as supported by the driver (read-only). + */ + struct drm_property *plane_shaper_lut_size_property; /** * @plane_lut3d_property: Plane property for gamma correction using a * 3D LUT (pre-blending). diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b0ba0279dc25..d3ecc73129ff 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -748,6 +748,11 @@ struct dm_plane_state { * S31.32 sign-magnitude. */ __u64 hdr_mult; + /** + * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an + * array of &struct drm_color_lut. + */ + struct drm_property_blob *shaper_lut; /** * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of * &struct drm_color_lut. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 0e418e161b0b..69e2f1f86cce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1347,6 +1347,8 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) #ifdef CONFIG_STEAM_DECK if (dm_plane_state->degamma_lut) drm_property_blob_get(dm_plane_state->degamma_lut); + if (dm_plane_state->shaper_lut) + drm_property_blob_get(dm_plane_state->shaper_lut); if (dm_plane_state->lut3d) drm_property_blob_get(dm_plane_state->lut3d); #endif @@ -1419,6 +1421,7 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); #ifdef CONFIG_STEAM_DECK drm_property_blob_put(dm_plane_state->degamma_lut); + drm_property_blob_put(dm_plane_state->shaper_lut); drm_property_blob_put(dm_plane_state->lut3d); #endif @@ -1495,6 +1498,11 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, AMDGPU_HDR_MULT_DEFAULT); if (dm->dc->caps.color.dpp.hw_3d_lut) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_shaper_lut_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_shaper_lut_size_property, + MAX_COLOR_LUT_ENTRIES); drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_lut3d_property, 0); drm_object_attach_property(&plane->base, @@ -1531,6 +1539,14 @@ dm_atomic_plane_set_property(struct drm_plane *plane, dm_plane_state->hdr_mult = val; dm_plane_state->base.color_mgmt_changed = 1; } + } else if (property == adev->mode_info.plane_shaper_lut_property) { + ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->shaper_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |= replaced; + return ret; } else if (property == adev->mode_info.plane_lut3d_property) { ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, &dm_plane_state->lut3d, @@ -1567,6 +1583,9 @@ dm_atomic_plane_get_property(struct drm_plane *plane, *val = dm_plane_state->degamma_tf; } else if (property == adev->mode_info.plane_hdr_mult_property) { *val = dm_plane_state->hdr_mult; + } else if (property == adev->mode_info.plane_shaper_lut_property) { + *val = (dm_plane_state->shaper_lut) ? + dm_plane_state->shaper_lut->base.id : 0; } else if (property == adev->mode_info.plane_lut3d_property) { *val = (dm_plane_state->lut3d) ? dm_plane_state->lut3d->base.id : 0;