From patchwork Sun Apr 23 14:10:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 86740 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2223025vqo; Sun, 23 Apr 2023 07:28:32 -0700 (PDT) X-Google-Smtp-Source: AKy350Z1utXIZwQHlCmjnFnK5CV3IzRqL5fkmwjJ+4GVlQ4QptFkJF8xAg8g01iZdVy7rj0/2CxR X-Received: by 2002:a17:902:d591:b0:1a6:b2e3:5dc4 with SMTP id k17-20020a170902d59100b001a6b2e35dc4mr10288436plh.14.1682260112486; Sun, 23 Apr 2023 07:28:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682260112; cv=none; d=google.com; s=arc-20160816; b=cB5H7k9p1ZdoBLPAJgjgf9kYWRBgb5taweI4rBZtywnaiYj8khaKmpbGDo9YvxhMc7 h0v5F7GAL1cxP+VuNCo1uzSJyo63f10hL1IFw9gzccy7j98sIzP8VhqLSTQZ4I6B+H5l 2rAoeXEIV6OpFo7Yj9OlevaR5beSi1l/VWPNu15JVd+2e4lA4HqwGWjw+w4VO0p0COyY qT5qfGv4B6NMGbRmKO+y+i3gE/EX5OLWlRQraRXGlJo4hkgEOlCKt/zbyB+Twpl7i9nA XuHUEyaeN13B7UbklXKwgI79jdA8dpXB9J+EXYSKfN8P0MTDC6sPJo1L1RxFI5FrwdXL fORQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AAZ5sTWcL6d1F4he+h8JfjtWQIRJ5weYPHqgnNEExCI=; b=S67jl4cuflXvsPLF8/cPli8sU0usN/qdYgTnquuFitAhANe7ncTCCz6y4MFGF3I++S 85ms8vGtQIP6S/2jnr6OuOt6Qvnb0sQThWBsFhsHO3JOe1eicRrQ2fvVQ9cK4ST5q3vZ /ILWIIOI8Gx2xwnoLH7IUrsiJQd7K7EUI2qkysWMvMEpkiyy7S7EHhDhhynIfeRL312H 3XMGrhr9SAbote5p+cPf5fecx2V4ZnhZUads0yrO3tAa/OqTMWU0gco4ZveHiB+kLZ7W rinMtmDB8POMwQAYPKHDz361LPMtnyhTwdwBKivbm1Jr1Yjm8AuIRMPTrnQB2q4QexMe Kknw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="gZIKjW/5"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e5-20020a17090301c500b0019c354055d0si9572096plh.304.2023.04.23.07.28.17; Sun, 23 Apr 2023 07:28:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b="gZIKjW/5"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230009AbjDWONb (ORCPT + 99 others); Sun, 23 Apr 2023 10:13:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229749AbjDWONX (ORCPT ); Sun, 23 Apr 2023 10:13:23 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C90B91FDF for ; Sun, 23 Apr 2023 07:12:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=AAZ5sTWcL6d1F4he+h8JfjtWQIRJ5weYPHqgnNEExCI=; b=gZIKjW/5GVEjC1IrACr56Fi8tZ ACTVa/+kOaJqEB5Jev/ClLObH/ZmOOTJ6QtyJAaeDWG/A9uc1EI80NLMoTgC53sorKOtT7uBDGvAd zixe1i8FPGQ5J8WZVUoRescfFFZm6H12wRhwtqOme9GAvUw6Cp2Yn6hbfAKqOXedP2yC6b+P39IVx kjb2ljiKk+Lx6F1FY0dCIp1A8wbcX1dfj7YM5+6/KGbmfRGUoKZd7eLxyL396LN637nE5sOKvsbJn yQMvdGKIA+hUOCpzX7H9aB4rQ2r4XsaU+91m3a65dQLWM3mpLeuiQu2esYmvI4R8JhsIQW4J1LCXT CdWOkNGA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaS3-00ANVs-Ka; Sun, 23 Apr 2023 16:12:27 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 10/40] drm/amd/display: add plane degamma LUT driver-private props Date: Sun, 23 Apr 2023 13:10:22 -0100 Message-Id: <20230423141051.702990-11-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763977579823801569?= X-GMAIL-MSGID: =?utf-8?q?1763977579823801569?= From: Joshua Ashton Create driver-private properties (not DRM KMS generic) for plane degamma LUT (user-blob and its size). Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 +++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 11 +++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 78 ++++++++++++++++++- 4 files changed, 111 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 1913903cab88..996c9c3fd471 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1303,6 +1303,20 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev) return -ENOMEM; adev->mode_info.gamma_tf_property = prop; + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_DEGAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_lut_property = prop; + + prop = drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_DEGAMMA_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_lut_size_property = prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 76337e18c728..d4e609a8b67e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -372,6 +372,16 @@ struct amdgpu_mode_info { * @gamma_tf_property: Transfer function for CRTC regamma. */ struct drm_property *gamma_tf_property; + /** + * @plane_degamma_lut_property: Plane property to set a degamma LUT to + * convert color space before blending. + */ + struct drm_property *plane_degamma_lut_property; + /** + * @plane_degamma_lut_size_property: Plane property to define the max + * size of degamma LUT as supported by the driver (read-only). + */ + struct drm_property *plane_degamma_lut_size_property; #endif }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 1e90a2dd445e..b1d0c65d821d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -719,6 +719,17 @@ enum drm_transfer_function { struct dm_plane_state { struct drm_plane_state base; struct dc_plane_state *dc_state; + +#ifdef CONFIG_STEAM_DECK + /* Plane color mgmt */ + /** + * @degamma_lut: + * + * LUT for converting plane pixel data before going into plane merger. + * The blob (if not NULL) is an array of &struct drm_color_lut. + */ + struct drm_property_blob *degamma_lut; +#endif }; struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 4e5498153be2..7b9d62c70b30 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1337,7 +1337,10 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) dm_plane_state->dc_state = old_dm_plane_state->dc_state; dc_plane_state_retain(dm_plane_state->dc_state); } - +#ifdef CONFIG_STEAM_DECK + if (dm_plane_state->degamma_lut) + drm_property_blob_get(dm_plane_state->degamma_lut); +#endif return &dm_plane_state->base; } @@ -1404,7 +1407,9 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) { struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - +#ifdef CONFIG_STEAM_DECK + drm_property_blob_put(dm_plane_state->degamma_lut); +#endif if (dm_plane_state->dc_state) dc_plane_state_release(dm_plane_state->dc_state); @@ -1444,6 +1449,68 @@ amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, return 0; } + +static void +dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, + struct drm_plane *plane) +{ + if (dm->dc->caps.color.dpp.dgam_ram || dm->dc->caps.color.dpp.gamma_corr ) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_lut_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + } +} + +static int +dm_atomic_plane_set_property(struct drm_plane *plane, + struct drm_plane_state *state, + struct drm_property *property, uint64_t val) +{ + struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); + struct amdgpu_device *adev = drm_to_adev(plane->dev); + bool replaced = false; + int ret; + + if (property == adev->mode_info.plane_degamma_lut_property) { + ret = amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->degamma_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |= replaced; + return ret; + } else { + drm_dbg_atomic(plane->dev, + "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", + plane->base.id, plane->name, + property->base.id, property->name); + return -EINVAL; + } + + return 0; +} + +static int +dm_atomic_plane_get_property(struct drm_plane *plane, + const struct drm_plane_state *state, + struct drm_property *property, + uint64_t *val) + +{ + struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); + struct amdgpu_device *adev = drm_to_adev(plane->dev); + + if (property == adev->mode_info.plane_degamma_lut_property) { + *val = (dm_plane_state->degamma_lut) ? + dm_plane_state->degamma_lut->base.id : 0; + } else { + return -EINVAL; + } + + return 0; +} #endif static const struct drm_plane_funcs dm_plane_funcs = { @@ -1454,6 +1521,10 @@ static const struct drm_plane_funcs dm_plane_funcs = { .atomic_duplicate_state = dm_drm_plane_duplicate_state, .atomic_destroy_state = dm_drm_plane_destroy_state, .format_mod_supported = dm_plane_format_mod_supported, +#ifdef CONFIG_STEAM_DECK + .atomic_set_property = dm_atomic_plane_set_property, + .atomic_get_property = dm_atomic_plane_get_property, +#endif }; int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, @@ -1524,6 +1595,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_helper_add(plane, &dm_plane_helper_funcs); +#ifdef CONFIG_STEAM_DECK + dm_plane_attach_color_mgmt_properties(dm, plane); +#endif /* Create (reset) the plane state */ if (plane->funcs->reset) plane->funcs->reset(plane);