arm64: dts: mediatek: add missing cache properties
Commit Message
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Please take the patch via sub-arch SoC tree.
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 2 ++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++
4 files changed, 7 insertions(+)
Comments
On 22/04/2023 00:31, Krzysztof Kozlowski wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified properties to fix warnings like:
>
> mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
Hi Matthias,
Could you grab this one?
Best regards,
Krzysztof
On 16/05/2023 18:32, Krzysztof Kozlowski wrote:
> On 22/04/2023 00:31, Krzysztof Kozlowski wrote:
>> As all level 2 and level 3 caches are unified, add required
>> cache-unified properties to fix warnings like:
>>
>> mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> ---
>
> Hi Matthias,
>
> Could you grab this one?
>
Applied now, thanks!
@@ -101,6 +101,7 @@ cpu1: cpu@1 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -250,6 +250,7 @@ l2_0: l2-cache0 {
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_0>;
+ cache-unified;
};
l2_1: l2-cache1 {
@@ -259,6 +260,7 @@ l2_1: l2-cache1 {
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_0>;
+ cache-unified;
};
l3_0: l3-cache {
@@ -228,6 +228,7 @@ l2_0: l2-cache0 {
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_0>;
+ cache-unified;
};
l2_1: l2-cache1 {
@@ -237,6 +238,7 @@ l2_1: l2-cache1 {
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_0>;
+ cache-unified;
};
l3_0: l3-cache {
@@ -283,6 +283,7 @@ l2_0: l2-cache0 {
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_0>;
+ cache-unified;
};
l2_1: l2-cache1 {
@@ -292,6 +293,7 @@ l2_1: l2-cache1 {
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_0>;
+ cache-unified;
};
l3_0: l3-cache {