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[2620:137:e000::1:20]) by mx.google.com with ESMTP id q12-20020a67f04c000000b0042e789b4801si1068657vsm.706.2023.04.21.10.03.34; Fri, 21 Apr 2023 10:03:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="C+L/41O8"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233504AbjDUQwH (ORCPT + 99 others); Fri, 21 Apr 2023 12:52:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233360AbjDUQvK (ORCPT ); Fri, 21 Apr 2023 12:51:10 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9516A15600; Fri, 21 Apr 2023 09:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682095856; x=1713631856; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zOQMasU7O3ApDraDZEqE3fWIuTTvJXbEyrdSDU+BbJk=; b=C+L/41O8W+Ql66Bd3oHRbXRnnfsUMCCviwbO0sdYggpV2SU7mq3B/1WZ VOdTjXD+T7YrGCloLdclY4US6bUwgV8spYY0aSr8fyf3YnKYXqgPe1Rkx P6g671RbXhW6vdcQhSWkrGVZJo9gB0ymFNtQJO0gor5LvQfvN9i/WvqDv 55TDbMrUM2S6fqEPz6PX2kKrecKvNTFAOQScfinNEu+JwykD4/S25BJh5 7Bvtel2utNY2Q/9vuRJGZkHul0fna+MyWGV8pAm4pIrQ+enOUjtvb46wo WX1I9GEtEdIGh3pm2T6ufBGWx7Nb+Z7mnm1EBdXcNPHJmO3TjxUsrUncY Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10687"; a="344786991" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="344786991" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 09:50:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10687"; a="722817378" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722817378" Received: from embargo.jf.intel.com ([10.165.9.183]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 09:50:42 -0700 From: Yang Weijiang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, john.allen@amd.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: rick.p.edgecombe@intel.com, weijiang.yang@intel.com, Sean Christopherson Subject: [PATCH v2 06/21] KVM:x86: Report XSS as to-be-saved if there are supported features Date: Fri, 21 Apr 2023 09:46:00 -0400 Message-Id: <20230421134615.62539-7-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230421134615.62539-1-weijiang.yang@intel.com> References: <20230421134615.62539-1-weijiang.yang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DATE_IN_PAST_03_06, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763806155830925958?= X-GMAIL-MSGID: =?utf-8?q?1763806155830925958?= From: Sean Christopherson Add MSR_IA32_XSS to the list of MSRs reported to userspace if supported_xss is non-zero, i.e. KVM supports at least one XSS based feature. Signed-off-by: Sean Christopherson Signed-off-by: Yang Weijiang --- arch/x86/kvm/x86.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e7f78fe79b32..33a780fe820b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1454,6 +1454,7 @@ static const u32 msrs_to_save_base[] = { MSR_IA32_UMWAIT_CONTROL, MSR_IA32_XFD, MSR_IA32_XFD_ERR, + MSR_IA32_XSS, }; static const u32 msrs_to_save_pmu[] = {