| Message ID | 20230419211856.79332-14-krzysztof.kozlowski@linaro.org |
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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<angelogioacchino.delregno@collabora.com>,
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Abel Vesa <abel.vesa@linaro.org>,
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linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH 14/18] arm64: dts: qcom: sm8350: correct PCI phy unit address
Date: Wed, 19 Apr 2023 23:18:52 +0200
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| Series |
[01/18] arm64: dts: qcom: ipq6018: correct qrng unit address
|
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Commit Message
Krzysztof Kozlowski
April 19, 2023, 9:18 p.m. UTC
Match unit-address to reg entry to fix dtbs W=1 warnings:
Warning (simple_bus_reg): /soc@0/phy@1c0f000: simple-bus unit address format error, expected "1c0e000"
Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On 19.04.2023 23:18, Krzysztof Kozlowski wrote: > Match unit-address to reg entry to fix dtbs W=1 warnings: > > Warning (simple_bus_reg): /soc@0/phy@1c0f000: simple-bus unit address format error, expected "1c0e000" > > Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices") > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index a9af730e0b1c..5ca21cd1cbec 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -1638,7 +1638,7 @@ pcie1: pci@1c08000 { > status = "disabled"; > }; > > - pcie1_phy: phy@1c0f000 { > + pcie1_phy: phy@1c0e000 { > compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; > reg = <0 0x01c0e000 0 0x2000>; > clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a9af730e0b1c..5ca21cd1cbec 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1638,7 +1638,7 @@ pcie1: pci@1c08000 { status = "disabled"; }; - pcie1_phy: phy@1c0f000 { + pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; reg = <0 0x01c0e000 0 0x2000>; clocks = <&gcc GCC_PCIE_1_AUX_CLK>,