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Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- .../soc/foobar/foobar,memory-controller.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/foobar/foobar,memory-controller.yaml diff --git a/Documentation/devicetree/bindings/soc/foobar/foobar,memory-controller.yaml b/Documentation/devicetree/bindings/soc/foobar/foobar,memory-controller.yaml new file mode 100644 index 000000000000..859ee52680d5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/foobar/foobar,memory-controller.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/foobar/foobar,memory-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Foobar SoC Memory Controller + +maintainers: + - Drew Fustini + +description: + Foobar SoC memory controller implements the RISC-V CBQRI interface for + capacity allocaiton and usage monitoring. + +allOf: + - $ref: /schemas/riscv/riscv,cbqri.yaml# + +properties: + compatible: + items: + - const: foobar,memory-controller + reg: + maxItems: 1 + description: A memory region containing registers as defined in CBQRI spec + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + memory-controller@fff12000 { + compatible = "foobar,memory-controller"; + reg = <0xfff12000 0x2000>; + riscv,cbqri-rcid = <64>; + riscv,cbqri-mcid = <256>; + }; + +...