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[62.216.205.204]) by smtp.googlemail.com with ESMTPSA id j23-20020a1709066c1700b0095342bfb701sm63259ejr.16.2023.04.18.10.26.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 10:26:24 -0700 (PDT) From: Johannes Thumshirn To: Wim Van Sebroeck , Guenter Roeck Cc: linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Johannes Thumshirn Subject: [PATCH 2/2] watchdog: menz069_wdt: fix timeout setting Date: Tue, 18 Apr 2023 19:25:31 +0200 Message-Id: <20230418172531.177349-3-jth@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230418172531.177349-1-jth@kernel.org> References: <20230418172531.177349-1-jth@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763536048758880230?= X-GMAIL-MSGID: =?utf-8?q?1763536048758880230?= When setting the timeout for the menz069_wdt watchdog driver, we erroneously read from the 'watchdog value register' (WVR) instead of the 'watchdog timer register' (WTR) and then write the value back into WTR. This can potentially lead to wrong timeouts and wrong enable bit settings. Signed-off-by: Johannes Thumshirn Reviewed-by: Guenter Roeck --- drivers/watchdog/menz69_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/menz69_wdt.c b/drivers/watchdog/menz69_wdt.c index bca0938f3429..3c98030b9fcd 100644 --- a/drivers/watchdog/menz69_wdt.c +++ b/drivers/watchdog/menz69_wdt.c @@ -77,7 +77,7 @@ static int men_z069_wdt_set_timeout(struct watchdog_device *wdt, wdt->timeout = timeout; val = timeout * MEN_Z069_TIMER_FREQ; - reg = readw(drv->base + MEN_Z069_WVR); + reg = readw(drv->base + MEN_Z069_WTR); ena = reg & MEN_Z069_WTR_WDEN; reg = ena | val; writew(reg, drv->base + MEN_Z069_WTR);