From patchwork Mon Apr 17 22:37:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 84494 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2446024vqo; Mon, 17 Apr 2023 15:43:05 -0700 (PDT) X-Google-Smtp-Source: AKy350ZATB7R1RNxh9h8jSLh4gf7ulu4gUKa/bh4+4inas/Yn3rtOgQ8+ZZwoiX7CIIGLlNeJOcW X-Received: by 2002:a17:902:db0e:b0:1a1:ca4d:120a with SMTP id m14-20020a170902db0e00b001a1ca4d120amr128573plx.7.1681771385629; Mon, 17 Apr 2023 15:43:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681771385; cv=none; d=google.com; s=arc-20160816; b=FRzzrF7JncDG/CDRAWn5wH8OJ+mLTlwMhRmMtI0fHlp7yC9o3HvXZmujIieCdowrFu YK6cgQHv2O02b7sPmEoUmq4/hg7uOQWr4AOaPHDvBCNm7M6LhJf4FElnUpfJfovsTfc3 VKT9SnHepiLl0u/jltrAWK6mVl9YAWkv8M6DNCUU1RHKnx7/7nY2qRzo4QvFywtNEYbM 5f670biSJRutB8cVtOFGbZElLcTRxZQt8i9WOpw6rdJqcZlu553LnwZvpLyKeQZw+Y8u BXmgesXjntQsxsSl10N48CF/yoxU28Bg1J2sjCZACddmYB1Aogw4Ot7ZIPC7ZAlFGjyz xcXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=gm1bVqW/yNereBzZ/Ev/KXEwJUyqK/wAFEsQlioQv1s=; b=Tj8K7dO02KpCQb7JAex7tQuLJlm/yqF4koE4FvZqslM401dwrxMCxBImGEuXw/rnbS pF6oZQFj1+896RIY5kHle/t2rkBxfdrjjLsot3J0rjWeHQvEtp8bu/O6At5uUYgFPDzn lnmONAi+gJKGH8cFeHSPbJpCer6NNSTwCo+C1snj4MkQqSr2DGBnsR7TqfgxsW6d2aRF x7wflG+KM5p/BP4gD28gLuZbHHYqja0bdFTLtAFNrtVOaCnlCPv9iM6xtH1Yf/k0z6jY +wGIcYlNUWcv579rMCLyeD4eE+GTK96bv/fJXi/ZEWeFw+u7lzhiiXiLe7DVKG+AUQ7q FA6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="hb/S2y/r"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a8-20020a17090a8c0800b00246973aef88si15068566pjo.29.2023.04.17.15.42.48; Mon, 17 Apr 2023 15:43:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="hb/S2y/r"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229604AbjDQWhs (ORCPT + 99 others); Mon, 17 Apr 2023 18:37:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229479AbjDQWhr (ORCPT ); Mon, 17 Apr 2023 18:37:47 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 065C14211; Mon, 17 Apr 2023 15:37:46 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 95401622A0; Mon, 17 Apr 2023 22:37:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B68D1C433D2; Mon, 17 Apr 2023 22:37:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681771064; bh=4chkLext4acUulDFIohP7fhi352aObb1FKu9YKPstuE=; h=From:To:Cc:Subject:Date:From; b=hb/S2y/rigkJ/WkHNx0ib5MgI+9jzdccld4y2a7WmRgQJTQxWBrKxMP7/1migDa+l mpaq8omKobu5mJmldMLps29p1NJnyNs9tF06dbKH50Gf/FWwxCNxCIZC9Wb2i4Aacc Hffx1HHVTZmFhpypOzI0iUqXs2HyHvycFwhhVMz5NxqyGcm2k3IsYslMRfLclnOnHS W5tCxT5Sn5+0XBEmLmszFqMLEMG/odozdGjLAhawRNwFc5T66v4nnxd9kxCRYIx0mR 5Va296OoFxxavFwIfnj8iln4VasY8gtLAKkmXCSCyrSGOdvr7nulYgpfX4ffysEdj8 NY0G9CU4mBtiQ== From: Arnd Bergmann To: Laurent Pinchart , Mauro Carvalho Chehab , Shawn Guo , Sascha Hauer , Christian Hemp , Dong Aisheng , Stefan Riedmueller Cc: Arnd Bergmann , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Jacopo Mondi , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] media: nxp: imx8-isi: fix buiding on 32-bit Date: Tue, 18 Apr 2023 00:37:27 +0200 Message-Id: <20230417223738.1811110-1-arnd@kernel.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763465112200213195?= X-GMAIL-MSGID: =?utf-8?q?1763465112200213195?= From: Arnd Bergmann The #if check is wrong, leading to a build failure: drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c: In function 'mxc_isi_channel_set_inbuf': drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c:33:5: error: "CONFIG_ARCH_DMA_ADDR_T_64BIT" is not defined, evaluates to 0 [-Werror=undef] 33 | #if CONFIG_ARCH_DMA_ADDR_T_64BIT | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ This could just be an #ifdef, but it seems nicer to just remove the check entirely. Apparently the only reason for the #ifdef is to avoid another warning: drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c:55:24: error: right shift count >= width of type [-Werror=shift-count-overflow] But this is best avoided by using the lower_32_bits()/upper_32_bits() helpers. Fixes: cf21f328fcaf ("media: nxp: Add i.MX8 ISI driver") Signed-off-by: Arnd Bergmann Reviewed-by: Laurent Pinchart --- .../media/platform/nxp/imx8-isi/imx8-isi-hw.c | 41 ++++++++++--------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c index db538f3d88ec..f6112b83866a 100644 --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c @@ -29,11 +29,10 @@ static inline void mxc_isi_write(struct mxc_isi_pipe *pipe, u32 reg, u32 val) void mxc_isi_channel_set_inbuf(struct mxc_isi_pipe *pipe, dma_addr_t dma_addr) { - mxc_isi_write(pipe, CHNL_IN_BUF_ADDR, dma_addr); -#if CONFIG_ARCH_DMA_ADDR_T_64BIT + mxc_isi_write(pipe, CHNL_IN_BUF_ADDR, lower_32_bits(dma_addr)); if (pipe->isi->pdata->has_36bit_dma) - mxc_isi_write(pipe, CHNL_IN_BUF_XTND_ADDR, dma_addr >> 32); -#endif + mxc_isi_write(pipe, CHNL_IN_BUF_XTND_ADDR, + upper_32_bits(dma_addr)); } void mxc_isi_channel_set_outbuf(struct mxc_isi_pipe *pipe, @@ -45,34 +44,36 @@ void mxc_isi_channel_set_outbuf(struct mxc_isi_pipe *pipe, val = mxc_isi_read(pipe, CHNL_OUT_BUF_CTRL); if (buf_id == MXC_ISI_BUF1) { - mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_Y, dma_addrs[0]); - mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_U, dma_addrs[1]); - mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_V, dma_addrs[2]); -#if CONFIG_ARCH_DMA_ADDR_T_64BIT + mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_Y, + lower_32_bits(dma_addrs[0])); + mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_U, + lower_32_bits(dma_addrs[1])); + mxc_isi_write(pipe, CHNL_OUT_BUF1_ADDR_V, + lower_32_bits(dma_addrs[2])); if (pipe->isi->pdata->has_36bit_dma) { mxc_isi_write(pipe, CHNL_Y_BUF1_XTND_ADDR, - dma_addrs[0] >> 32); + upper_32_bits(dma_addrs[0])); mxc_isi_write(pipe, CHNL_U_BUF1_XTND_ADDR, - dma_addrs[1] >> 32); + upper_32_bits(dma_addrs[1])); mxc_isi_write(pipe, CHNL_V_BUF1_XTND_ADDR, - dma_addrs[2] >> 32); + upper_32_bits(dma_addrs[2])); } -#endif val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR; } else { - mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_Y, dma_addrs[0]); - mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_U, dma_addrs[1]); - mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_V, dma_addrs[2]); -#if CONFIG_ARCH_DMA_ADDR_T_64BIT + mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_Y, + lower_32_bits(dma_addrs[0])); + mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_U, + lower_32_bits(dma_addrs[1])); + mxc_isi_write(pipe, CHNL_OUT_BUF2_ADDR_V, + lower_32_bits(dma_addrs[2])); if (pipe->isi->pdata->has_36bit_dma) { mxc_isi_write(pipe, CHNL_Y_BUF2_XTND_ADDR, - dma_addrs[0] >> 32); + upper_32_bits(dma_addrs[0])); mxc_isi_write(pipe, CHNL_U_BUF2_XTND_ADDR, - dma_addrs[1] >> 32); + upper_32_bits(dma_addrs[1])); mxc_isi_write(pipe, CHNL_V_BUF2_XTND_ADDR, - dma_addrs[2] >> 32); + upper_32_bits(dma_addrs[2])); } -#endif val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR; }