Message ID | 20230417082127.11681-4-quic_tdas@quicinc.com |
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State | New |
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Mon, 17 Apr 2023 08:23:06 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33H8N5Wr024522 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 17 Apr 2023 08:23:05 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Mon, 17 Apr 2023 01:23:01 -0700 From: Taniya Das <quic_tdas@quicinc.com> To: Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, "Bjorn Andersson" <andersson@kernel.org>, Andy Gross <agross@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org> CC: <dmitry.baryshkov@linaro.org>, <quic_skakitap@quicinc.com>, <quic_jkona@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Taniya Das <quic_tdas@quicinc.com> Subject: [PATCH V2 3/3] arm64: dts: qcom: sm8450: Add video clock controller Date: Mon, 17 Apr 2023 13:51:27 +0530 Message-ID: <20230417082127.11681-4-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230417082127.11681-1-quic_tdas@quicinc.com> References: <20230417082127.11681-1-quic_tdas@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: EusM-uAA01ZUD0GxnyKM5v2RCpRIf9-l X-Proofpoint-ORIG-GUID: EusM-uAA01ZUD0GxnyKM5v2RCpRIf9-l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-17_04,2023-04-14_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 bulkscore=0 mlxlogscore=860 adultscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304170074 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763411888854307953?= X-GMAIL-MSGID: =?utf-8?q?1763411888854307953?= |
Series |
Add video clock controller driver for SM8450
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Commit Message
Taniya Das
April 17, 2023, 8:21 a.m. UTC
Add device node for video clock controller on Qualcomm SM8450 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
Changes since V1:
- No changes.
arch/arm64/boot/dts/qcom/sm8450.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 31877f18dce2..863a39000630 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -760,6 +760,19 @@ gcc: clock-controller@100000 { "usb3_phy_wrapper_gcc_usb30_pipe_clk"; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo", "iface"; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>;