diff mbox series

[V2,1/4] dt-bindings: clock: qcom,ipq9574-gcc: Drop bias_pll_ubi_nc_clk input

Message ID 20230417053355.25691-2-quic_devipriy@quicinc.com
State New
Headers
Series Incremental patches on minimal boot support |

Commit Message

Devi Priya April 17, 2023, 5:33 a.m. UTC 
  Drop unused bias_pll_ubi_nc_clk input to the clock controller.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 Changes since V9:
	- Dropped the unused bias_pll_ubi_nc_clk input
	- Added Bjorn Andersson to the maintainers list

 Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Comments

Krzysztof Kozlowski April 19, 2023, 6:01 p.m. UTC | #1 
On 17/04/2023 07:33, Devi Priya wrote:
> Drop unused bias_pll_ubi_nc_clk input to the clock controller.
> 
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>  Changes since V9:
> 	- Dropped the unused bias_pll_ubi_nc_clk input
> 	- Added Bjorn Andersson to the maintainers list


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
index afc68eb9d7cc..8581de266750 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
@@ -7,6 +7,7 @@  $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Global Clock & Reset Controller on IPQ9574
 
 maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
   - Anusha Rao <quic_anusha@quicinc.com>
 
 description: |
@@ -25,7 +26,6 @@  properties:
     items:
       - description: Board XO source
       - description: Sleep clock source
-      - description: Bias PLL ubi clock source
       - description: PCIE30 PHY0 pipe clock source
       - description: PCIE30 PHY1 pipe clock source
       - description: PCIE30 PHY2 pipe clock source
@@ -48,7 +48,6 @@  examples:
       reg = <0x01800000 0x80000>;
       clocks = <&xo_board_clk>,
                <&sleep_clk>,
-               <&bias_pll_ubi_nc_clk>,
                <&pcie30_phy0_pipe_clk>,
                <&pcie30_phy1_pipe_clk>,
                <&pcie30_phy2_pipe_clk>,