[v2,3/4] dt-bindings: clock: Add gate-clock

Message ID 20230416173302.1185683-4-mmyangfl@gmail.com
State New
Headers
Series clk: Add basic register clock controller |

Commit Message

Yangfl April 16, 2023, 5:33 p.m. UTC
  Add DT bindings documentation for gate-clock, which can gate its output.

Signed-off-by: David Yang <mmyangfl@gmail.com>
---
 .../devicetree/bindings/clock/gate-clock.yaml | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/gate-clock.yaml
  

Comments

Krzysztof Kozlowski April 16, 2023, 5:41 p.m. UTC | #1
On 16/04/2023 19:33, David Yang wrote:
> Add DT bindings documentation for gate-clock, which can gate its output.
> 
> Signed-off-by: David Yang <mmyangfl@gmail.com>
> ---
>  .../devicetree/bindings/clock/gate-clock.yaml | 58 +++++++++++++++++++
>  1 file changed, 58 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/gate-clock.yaml

Where is the changelog? What happened here?

> 
> diff --git a/Documentation/devicetree/bindings/clock/gate-clock.yaml b/Documentation/devicetree/bindings/clock/gate-clock.yaml
> new file mode 100644
> index 000000000000..3c993cb7e9bb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/gate-clock.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/gate-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Clock which can gate its output
> +
> +maintainers:
> +  - David Yang <mmyangfl@gmail.com>
> +
> +description: |
> +  Clock which can gate its output.
> +
> +  The registers map is retrieved from the parental dt-node. So the clock node
> +  should be represented as a sub-node of a "clock-controller" node.

If this is supposed to be used in parent schema, then reference it there.

> +
> +  See also: linux/clk-provider.h

How is this related to hardware? Also, referencing linux headers is
usually not good idea for bindings.
> +
> +properties:
> +  compatible:
> +    const: gate-clock
> +
> +  '#clock-cells':
> +    const: 0
> +
> +  clocks:
> +    maxItems: 1
> +    description: Parent clock.
> +
> +  offset:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: Offset in the register map for the control register (in bytes).
> +
> +  bits:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: Bit index which controls the output.
> +
> +  clock-output-names:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - '#clock-cells'
> +  - offset
> +  - bits
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    gate-clock@cc.3 {

So you keep ignoring the comments... I don't know what happened here but
this code for sure looks wrong.

Did you test the changes?

Best regards,
Krzysztof
  
Yangfl April 16, 2023, 6:28 p.m. UTC | #2
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 于2023年4月17日周一 01:41写道:
>
> Did you test the changes?

I don't know what "test" is here. make dt_binding_check passed and it
can work with the driver.
  
Krzysztof Kozlowski April 16, 2023, 6:31 p.m. UTC | #3
On 16/04/2023 20:28, Yangfl wrote:
> Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 于2023年4月17日周一 01:41写道:
>>
>> Did you test the changes?
> 
> I don't know what "test" is here. make dt_binding_check passed and it
> can work with the driver.

I don't think so. If you tested it, for sure you would see warnings like
"node has a unit name, but no reg or ranges property".

Best regards,
Krzysztof
  

Patch

diff --git a/Documentation/devicetree/bindings/clock/gate-clock.yaml b/Documentation/devicetree/bindings/clock/gate-clock.yaml
new file mode 100644
index 000000000000..3c993cb7e9bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/gate-clock.yaml
@@ -0,0 +1,58 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/gate-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock which can gate its output
+
+maintainers:
+  - David Yang <mmyangfl@gmail.com>
+
+description: |
+  Clock which can gate its output.
+
+  The registers map is retrieved from the parental dt-node. So the clock node
+  should be represented as a sub-node of a "clock-controller" node.
+
+  See also: linux/clk-provider.h
+
+properties:
+  compatible:
+    const: gate-clock
+
+  '#clock-cells':
+    const: 0
+
+  clocks:
+    maxItems: 1
+    description: Parent clock.
+
+  offset:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Offset in the register map for the control register (in bytes).
+
+  bits:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Bit index which controls the output.
+
+  clock-output-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - '#clock-cells'
+  - offset
+  - bits
+
+additionalProperties: false
+
+examples:
+  - |
+    gate-clock@cc.3 {
+      compatible = "gate-clock";
+      #clock-cells = <0>;
+      offset = <0xcc>;
+      bits = <3>;
+      clock-output-names = "my-clk";
+    };