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Piccoli" , Piotr Gorski , Sabin Rapan , David Woodhouse , Usama Arif , Juergen Gross , Boris Ostrovsky , xen-devel@lists.xenproject.org, Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Guo Ren , linux-csky@vger.kernel.org, Thomas Bogendoerfer , linux-mips@vger.kernel.org, "James E.J. Bottomley" , Helge Deller , linux-parisc@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, Mark Rutland Subject: [patch 37/37] x86/smpboot: Allow parallel bringup for SEV-ES References: <20230414225551.858160935@linutronix.de> MIME-Version: 1.0 Date: Sat, 15 Apr 2023 01:45:13 +0200 (CEST) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763197690944901194?= X-GMAIL-MSGID: =?utf-8?q?1763197690944901194?= From: David Woodhouse Enable parallel bringup for SEV-ES guests. The APs can't actually execute the CPUID instruction directly during early startup, but they can make the GHCB call directly instead, just as the #VC trap handler would do. Thanks to Sabin for talking me through the way this works. Suggested-by: Sabin Rapan Signed-off-by: David Woodhouse Signed-off-by: Usama Arif Signed-off-by: Thomas Gleixner Reviewed-by: Tom Lendacky --- arch/x86/include/asm/sev-common.h | 3 +++ arch/x86/include/asm/smp.h | 1 + arch/x86/kernel/head_64.S | 30 ++++++++++++++++++++++++++++++ arch/x86/kernel/smpboot.c | 14 ++++++++++++-- 4 files changed, 46 insertions(+), 2 deletions(-) --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -70,6 +70,7 @@ /* GHCBData[63:12] */ \ (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) +#ifndef __ASSEMBLY__ /* * SNP Page State Change Operation * @@ -161,6 +162,8 @@ struct snp_psc_desc { #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) +#endif /* __ASSEMBLY__ */ + /* * Error codes related to GHCB input that can be communicated back to the guest * by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2. --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -202,6 +202,7 @@ extern unsigned int smpboot_control; #define STARTUP_APICID_CPUID_1F 0x80000000 #define STARTUP_APICID_CPUID_0B 0x40000000 #define STARTUP_APICID_CPUID_01 0x20000000 +#define STARTUP_APICID_SEV_ES 0x10000000 /* Top 8 bits are reserved for control */ #define STARTUP_PARALLEL_MASK 0xFF000000 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -26,6 +26,7 @@ #include #include #include +#include /* * We are not able to switch in one step to the final KERNEL ADDRESS SPACE @@ -243,9 +244,14 @@ SYM_INNER_LABEL(secondary_startup_64_no_ * Bit 31 STARTUP_APICID_CPUID_1F flag (use CPUID 0x1f) * Bit 30 STARTUP_APICID_CPUID_0B flag (use CPUID 0x0b) * Bit 29 STARTUP_APICID_CPUID_01 flag (use CPUID 0x01) + * Bit 28 STARTUP_APICID_SEV_ES flag (CPUID 0x0b via GHCB MSR) * Bit 0-23 CPU# if STARTUP_APICID_CPUID_xx flags are not set */ movl smpboot_control(%rip), %ecx +#ifdef CONFIG_AMD_MEM_ENCRYPT + testl $STARTUP_APICID_SEV_ES, %ecx + jnz .Luse_sev_cpuid_0b +#endif testl $STARTUP_APICID_CPUID_1F, %ecx jnz .Luse_cpuid_1f testl $STARTUP_APICID_CPUID_0B, %ecx @@ -262,6 +268,30 @@ SYM_INNER_LABEL(secondary_startup_64_no_ shr $24, %edx jmp .Lsetup_AP +#ifdef CONFIG_AMD_MEM_ENCRYPT +.Luse_sev_cpuid_0b: + /* Set the GHCB MSR to request CPUID 0x0B_EDX */ + movl $MSR_AMD64_SEV_ES_GHCB, %ecx + movl $(GHCB_CPUID_REQ_EDX << 30) | GHCB_MSR_CPUID_REQ, %eax + movl $0x0b, %edx + wrmsr + + /* Perform GHCB MSR protocol */ + rep; vmmcall /* vmgexit */ + + /* + * Get the result. After the RDMSR: + * EAX should be 0xc0000005 + * EDX should have the CPUID register value and since EDX + * is the target register, no need to move the result. + */ + rdmsr + andl $GHCB_MSR_INFO_MASK, %eax + cmpl $GHCB_MSR_CPUID_RESP, %eax + jne 1f + jmp .Lsetup_AP +#endif + .Luse_cpuid_0b: mov $0x0B, %eax xorl %ecx, %ecx --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -86,6 +86,7 @@ #include #include #include +#include /* representing HT siblings of each logical CPU */ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); @@ -1266,8 +1267,16 @@ bool __init arch_cpuhp_init_parallel_bri /* Encrypted guests require special CPUID handling. */ if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) { - pr_info("Parallel CPU startup disabled due to guest state encryption\n"); - return false; + switch (cc_get_vendor()) { + case CC_VENDOR_AMD: + ctrl = STARTUP_APICID_SEV_ES; + if (topology_extended_leaf == 0x0b) + goto setup; + fallthrough; + default: + pr_info("Parallel CPU startup disabled due to guest state encryption\n"); + return false; + } } switch (topology_extended_leaf) { @@ -1290,6 +1299,7 @@ bool __init arch_cpuhp_init_parallel_bri return false; } +setup: pr_debug("Parallel CPU startup enabled: 0x%08x\n", ctrl); smpboot_control = ctrl; return true;