Message ID | 20230414151553.339599-2-j-choudhary@ti.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m6-20020a17090a3f8600b00237dd21c1b7si675620pjc.143.2023.04.14.08.21.24; Fri, 14 Apr 2023 08:21:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=uAhDZDZg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231243AbjDNPQZ (ORCPT <rfc822;leviz.kernel.dev@gmail.com> + 99 others); Fri, 14 Apr 2023 11:16:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230498AbjDNPQU (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 14 Apr 2023 11:16:20 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2704B93CE; Fri, 14 Apr 2023 08:16:14 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33EFFuIi106038; Fri, 14 Apr 2023 10:15:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681485356; bh=gJwIOSAR6mPpOZd/TA9dQZe8R4GmfYpdvlq9WvMeFY0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uAhDZDZgTpZ4RPCZgrC6NW1YDRBseLCEivc6F1mXszjl9BOv02oqNu9KZLGs7tNXd xnkXq7LoZnWKyLRuHQe6dUEmbDaE2SnXZ+qt/jg4K1OIH2roHWJ4hQR2dpJ4iyhpJl ZSyWMBzAuYz3btEc4UaumTXpwzzkZ6G0fyDkTO1g= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33EFFuLd014101 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 14 Apr 2023 10:15:56 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 14 Apr 2023 10:15:55 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 14 Apr 2023 10:15:55 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33EFFt1M096145; Fri, 14 Apr 2023 10:15:55 -0500 From: Jayesh Choudhary <j-choudhary@ti.com> To: <nm@ti.com>, <vigneshr@ti.com>, <afd@ti.com> CC: <s-vadapalli@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <j-choudhary@ti.com> Subject: [PATCH v2 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Date: Fri, 14 Apr 2023 20:45:49 +0530 Message-ID: <20230414151553.339599-2-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414151553.339599-1-j-choudhary@ti.com> References: <20230414151553.339599-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763165548090830212?= X-GMAIL-MSGID: =?utf-8?q?1763165548090830212?= |
Series |
Add peripherals for J784S4
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Commit Message
Jayesh Choudhary
April 14, 2023, 3:15 p.m. UTC
From: Siddharth Vadapalli <s-vadapalli@ti.com> The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
Comments
Hi Jayesh On 14/04/23 20:45, Jayesh Choudhary wrote: > From: Siddharth Vadapalli <s-vadapalli@ti.com> > > The system controller node manages the CTRL_MMR0 region. > Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index e9169eb358c1..344f4ffa0b82 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -5,6 +5,9 @@ > * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ > */ > > +#include <dt-bindings/mux/mux.h> > +#include <dt-bindings/mux/ti-serdes.h> > + > &cbass_main { > msmc_ram: sram@70000000 { > compatible = "mmio-sram"; > @@ -26,6 +29,25 @@ l3cache-sram@200000 { > }; > }; > > + scm_conf: scm-conf@100000 { generic node name please: "syscon@" > + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; > + reg = <0x00 0x00100000 0x00 0x1c000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00 0x00 0x00100000 0x1c000>; > + > + serdes_ln_ctrl: mux-controller@4080 { Either add reg property or replace @ with - Run make with W=12 to catch such errors. > + compatible = "mmio-mux"; > + #mux-control-cells = <1>; > + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ > + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ > + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ > + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ > + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ > + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ > + }; > + }; > + > gic500: interrupt-controller@1800000 { > compatible = "arm,gic-v3"; > #address-cells = <2>;
Hi Vignesh, On 17/04/23 10:07, Vignesh Raghavendra wrote: > Hi Jayesh > > On 14/04/23 20:45, Jayesh Choudhary wrote: >> From: Siddharth Vadapalli <s-vadapalli@ti.com> >> >> The system controller node manages the CTRL_MMR0 region. >> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >> index e9169eb358c1..344f4ffa0b82 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >> @@ -5,6 +5,9 @@ >> * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ >> */ >> >> +#include <dt-bindings/mux/mux.h> >> +#include <dt-bindings/mux/ti-serdes.h> >> + >> &cbass_main { >> msmc_ram: sram@70000000 { >> compatible = "mmio-sram"; >> @@ -26,6 +29,25 @@ l3cache-sram@200000 { >> }; >> }; >> >> + scm_conf: scm-conf@100000 { > > generic node name please: "syscon@" Okay. > >> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; >> + reg = <0x00 0x00100000 0x00 0x1c000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x00 0x00 0x00100000 0x1c000>; >> + >> + serdes_ln_ctrl: mux-controller@4080 { > > Either add reg property or replace @ with - Will use '-'. > > Run make with W=12 to catch such errors. Okay. Will do. Thanks. [...]
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e9169eb358c1..344f4ffa0b82 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,9 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/mux/mux.h> +#include <dt-bindings/mux/ti-serdes.h> + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +29,25 @@ l3cache-sram@200000 { }; }; + scm_conf: scm-conf@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller@4080 { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>;