From patchwork Thu Apr 13 03:31:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cai Huoqing X-Patchwork-Id: 82746 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp762120vqo; Wed, 12 Apr 2023 20:43:52 -0700 (PDT) X-Google-Smtp-Source: AKy350YobZWvwDaX4F5nzcm3Em3cx3MiTMJ5fTAGHrS+Hl5PGVN2/8P8iLocnNjfKAxZXRWX50nB X-Received: by 2002:a05:6402:1010:b0:506:2c70:3066 with SMTP id c16-20020a056402101000b005062c703066mr1082855edu.21.1681357432103; Wed, 12 Apr 2023 20:43:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681357432; cv=none; d=google.com; s=arc-20160816; b=s+CGaVMx9fgCTV2g6RQppu2lb1GQMQchEVGQcZQ6W5mIkZWrI46mEtyoA3gaXmPbZL 77HdrqeN9JXATVwxQHFasy/1pPyrEOlOwp7xFew7Ue9YJSVQE4F/bXEa9jNjvbjOX5zf eoPqLdfhQb/NpYwPdbLgxEpV43lqCZfT6pfJEnpAd7Raeb9lw45VhKvQapwKHHK82rIH vpViNkBrUQQATgqDlEAqx5RwrJEeE/OU5Qshca8OLvj+w++YSIo7Vd5ZqePOVh337Pqo FeXI4xiFon20SdvyCX4/7xhPsFb3APhK/Gf7Qdnm9q6HvIw5lBYWzbVnMInIIZyb57B5 YDOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9ZqhxYkuLtJy75J90sFKhndIHhi/agv2yxX2a0SwSLo=; b=Y+mIIIgELFsWfEam2E8Gk4X8z6HQcKAHGfra+fUHWBOIjpMlG9m4NZwmvwxr2OzoTK LTZakpUM5EwkpimEOyYmnh8TLmmECiKgOokC1kxeB5yWs3TsdsFLacg7vF1FkPye1ov7 +wvzaazLfISKc3N939x2c3nz1dvs9usc13agoQAC011BsHfgy/iyjnO+GvqkQQxQcS6V 83EKVpOdaN/woRx9ZwoobnQsZJviT8FukFon7/TAV+a5ykHddidjd5EvTOji22Q+qyA6 xRgrM2ZrxLkkWq9XRphYw2cG50YSc1Wcl7xYabedcksmzAt9TlXVw1b0we6CW+Z/emCd wpRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linux.dev header.s=key1 header.b=OzfbaRUc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.dev Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r18-20020aa7da12000000b00504882a026fsi706176eds.78.2023.04.12.20.43.28; Wed, 12 Apr 2023 20:43:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linux.dev header.s=key1 header.b=OzfbaRUc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.dev Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229793AbjDMDcU (ORCPT + 99 others); Wed, 12 Apr 2023 23:32:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229736AbjDMDcM (ORCPT ); Wed, 12 Apr 2023 23:32:12 -0400 Received: from out-16.mta0.migadu.com (out-16.mta0.migadu.com [IPv6:2001:41d0:1004:224b::10]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCA1510C0 for ; Wed, 12 Apr 2023 20:32:09 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1681356728; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9ZqhxYkuLtJy75J90sFKhndIHhi/agv2yxX2a0SwSLo=; b=OzfbaRUc3G4xYYHuyTOaWBuTexucTFVI1pkFOGIRoDqBHcMrbX9KhHGidNFxGyBxITC4Yf Htwwn0MM7NK4AmVMnvfy/Tt/80+BgxfS4QxV4/XxQGNX0/GmNi3lHB/N1S84yQMJo5W1VD BtPwIXbL0MJ9jlUnRRYCv8w2OlIjKis= From: Cai Huoqing To: fancer.lancer@gmail.com Cc: Cai huoqing , Gustavo Pimentel , Vinod Koul , Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH RESEND v9 1/4] dmaengine: dw-edma: Rename dw_edma_core_ops structure to dw_edma_plat_ops Date: Thu, 13 Apr 2023 11:31:52 +0800 Message-Id: <20230413033156.93751-2-cai.huoqing@linux.dev> In-Reply-To: <20230413033156.93751-1-cai.huoqing@linux.dev> References: <20230413033156.93751-1-cai.huoqing@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763031050644340859?= X-GMAIL-MSGID: =?utf-8?q?1763031050644340859?= From: Cai huoqing The dw_edma_core_ops structure contains a set of the operations: device IRQ numbers getter, CPU/PCI address translation. Based on the functions semantics the structure name "dw_edma_plat_ops" looks more descriptive since indeed the operations are platform-specific. The "dw_edma_core_ops" name shall be used for a structure with the IP-core specific set of callbacks in order to abstract out DW eDMA and DW HDMA setups. Such structure will be added in one of the next commit in the framework of the set of changes adding the DW HDMA device support. Anyway the renaming was necessary to distinguish two types of the implementation callbacks: 1. DW eDMA/hDMA IP-core specific operations: device-specific CSR setups in one or another aspect of the DMA-engine initialization. 2. DW eDMA/hDMA platform specific operations: the DMA device environment configs like IRQs, address translation, etc. Signed-off-by: Cai huoqing Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam --- v8->v9: No change v8 link: https://lore.kernel.org/lkml/20230323034944.78357-2-cai.huoqing@linux.dev/ drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware.c | 2 +- include/linux/dma/edma.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 2b40f2b44f5e..1c6043751dc9 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -109,7 +109,7 @@ static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) return region.start; } -static const struct dw_edma_core_ops dw_edma_pcie_core_ops = { +static const struct dw_edma_plat_ops dw_edma_pcie_plat_ops = { .irq_vector = dw_edma_pcie_irq_vector, .pci_address = dw_edma_pcie_address, }; @@ -225,7 +225,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->mf = vsec_data.mf; chip->nr_irqs = nr_irqs; - chip->ops = &dw_edma_pcie_core_ops; + chip->ops = &dw_edma_pcie_plat_ops; chip->ll_wr_cnt = vsec_data.wr_ch_cnt; chip->ll_rd_cnt = vsec_data.rd_ch_cnt; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 8e33e6e59e68..1f2ee71da4da 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -828,7 +828,7 @@ static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) return platform_get_irq_byname_optional(pdev, name); } -static struct dw_edma_core_ops dw_pcie_edma_ops = { +static struct dw_edma_plat_ops dw_pcie_edma_ops = { .irq_vector = dw_pcie_edma_irq_vector, }; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index d2638d9259dc..ed401c965a87 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -40,7 +40,7 @@ struct dw_edma_region { * iATU windows. That will be done by the controller * automatically. */ -struct dw_edma_core_ops { +struct dw_edma_plat_ops { int (*irq_vector)(struct device *dev, unsigned int nr); u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr); }; @@ -80,7 +80,7 @@ enum dw_edma_chip_flags { struct dw_edma_chip { struct device *dev; int nr_irqs; - const struct dw_edma_core_ops *ops; + const struct dw_edma_plat_ops *ops; u32 flags; void __iomem *reg_base;