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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i14-20020a170902c94e00b001a1abc9198asi5327183pla.175.2023.04.12.06.34.41; Wed, 12 Apr 2023 06:34:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nwfD3+yM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229728AbjDLNYp (ORCPT + 99 others); Wed, 12 Apr 2023 09:24:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231540AbjDLNYQ (ORCPT ); Wed, 12 Apr 2023 09:24:16 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF3B25BB5; Wed, 12 Apr 2023 06:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681305823; x=1712841823; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F144WkXGDtgiQojUzaGHX2Gj+C/1Td/SdY0Sjd/5UtY=; b=nwfD3+yMzjnNm3HrQpHc6jUd6d/nNB7VhRyKyTWuYc3r2a9NELVEmfQ5 TpnLHU082oBlupPdBu0ViEtSR5O93xTu0rDDliUYJovMrrbYyNlX9uWiA FbZwNSHxbVDWMXTz8muYnO22lRrn1NLtxiUmUnxEtbY4A6APdQuB/CVAd n+oBOvU5r7xH8T1Xkxf3HH4ljzcTgyWQMMqJpL+WOzyu86490Cobw6XWS zj8ZEplHfdfHbadxSOSprSq4IB53zBBgLES1DpmTIReGV2WEgouPgO/qN NPt3eC1UwVKpHcbaPs5ZEsgBLe51lqE1KJz8EpN3X7UVXqLS2uL6FbFoX w==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="332590247" X-IronPort-AV: E=Sophos;i="5.98,339,1673942400"; d="scan'208";a="332590247" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 06:22:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="639230102" X-IronPort-AV: E=Sophos;i="5.98,339,1673942400"; d="scan'208";a="639230102" Received: from chanse1-mobl2.ger.corp.intel.com (HELO ijarvine-MOBL2.ger.corp.intel.com) ([10.251.213.80]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 06:22:40 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Reinette Chatre , Fenghua Yu , Shuah Khan Cc: Shaopeng Tan , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 16/22] selftests/resctrl: Exclude shareable bits from schemata in CAT test Date: Wed, 12 Apr 2023 16:21:16 +0300 Message-Id: <20230412132122.29452-17-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230412132122.29452-1-ilpo.jarvinen@linux.intel.com> References: <20230412132122.29452-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762977638742282968?= X-GMAIL-MSGID: =?utf-8?q?1762977638742282968?= CAT test doesn't take shareable bits into account, i.e., the test might be sharing cache with some devices (e.g., graphics). Introduce get_mask_no_shareable() and use it to provision an environment for CAT test where the allocated LLC is isolated better. Signed-off-by: Ilpo Järvinen --- tools/testing/selftests/resctrl/cat_test.c | 2 +- tools/testing/selftests/resctrl/resctrl.h | 3 ++ tools/testing/selftests/resctrl/resctrlfs.c | 56 +++++++++++++++++++++ 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c index ec73b2f1a82a..2b5333ad13bb 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -105,7 +105,7 @@ int cat_perf_miss_val(int cpu_no, int n, char *cache_type) return ret; /* Get default cbm mask for L3/L2 cache */ - ret = get_cbm_mask(cache_type, &long_mask); + ret = get_mask_no_shareable(cache_type, &long_mask); if (ret) return ret; count_of_bits = count_consecutive_bits(long_mask, NULL); diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h index 6d8ebdcec214..7609d5765fcd 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -108,8 +108,11 @@ void tests_cleanup(void); void mbm_test_cleanup(void); int mba_schemata_change(int cpu_no, char *bw_report, char **benchmark_cmd); void mba_test_cleanup(void); +unsigned long create_bit_mask(unsigned int start, unsigned int len); unsigned int count_consecutive_bits(unsigned long val, unsigned int *start); int get_cbm_mask(char *cache_type, unsigned long *mask); +int get_shareable_mask(char *cache_type, unsigned long *shareable_mask); +int get_mask_no_shareable(char *cache_type, unsigned long *mask); int get_cache_size(int cpu_no, char *cache_type, unsigned long *cache_size); int cache_alloc_size(int cpu_no, char *cache_type, unsigned long slice_mask, unsigned long *slice_size); diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/selftests/resctrl/resctrlfs.c index 28d6b594d8d9..0abe91ac9bd0 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -230,6 +230,16 @@ static int get_bit_mask(char *filename, unsigned long *mask) return 0; } +/* + * create_bit_mask- Create bit mask from start,len pair + * @start: LSB of the mask + * @len Number of bits in the mask + */ +unsigned long create_bit_mask(unsigned int start, unsigned int len) +{ + return ((1UL << len) - 1UL) << start; +} + /* * count_consecutive_bits - Returns the longest train of bits in a bit mask * @val A bit mask @@ -283,6 +293,52 @@ int get_cbm_mask(char *cache_type, unsigned long *mask) return 0; } +/* + * get_shareable_mask - Get shareable mask from shareable_bits for given cache + * @cache_type: Cache level L2/L3 + * @shareable_mask: shareable mask returned as unsigned long + * + * Return: = 0 on success, < 0 on failure. + */ +int get_shareable_mask(char *cache_type, unsigned long *shareable_mask) +{ + char mask_path[1024]; + + if (!cache_type) + return -1; + + snprintf(mask_path, sizeof(mask_path), "%s/%s/shareable_bits", + INFO_PATH, cache_type); + + return get_bit_mask(mask_path, shareable_mask); +} + +/* + * get_mask_no_shareable - Get CBM mask without shareable_bits for given cache + * @cache_type: Cache level L2/L3 + * @mask: mask returned as unsigned long + * + * Return: = 0 on success, < 0 on failure. + */ +int get_mask_no_shareable(char *cache_type, unsigned long *mask) +{ + unsigned long full_mask, shareable_mask; + unsigned int start, len; + + if (get_cbm_mask(cache_type, &full_mask) < 0) + return -1; + if (get_shareable_mask(cache_type, &shareable_mask) < 0) + return -1; + + len = count_consecutive_bits(full_mask & ~shareable_mask, &start); + if (!len) + return -1; + + *mask = create_bit_mask(start, len); + + return 0; +} + /* * get_core_sibling - Get sibling core id from the same socket for given CPU * @cpu_no: CPU number