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Mon, 10 Apr 2023 13:47:06 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v13 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Mon, 10 Apr 2023 11:45:20 -0700 Message-ID: <20230410184526.15990-10-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230410184526.15990-1-blarson@amd.com> References: <20230410184526.15990-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT032:EE_|SA1PR12MB8724:EE_ X-MS-Office365-Filtering-Correlation-Id: bfa20993-3530-46d4-acbb-08db39f3fd85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uI9FOduZ3iiJaZSLmz23XTT1UsyGR8PAHV1x9D3cH1hoZnrAsORD8AxZC5ybtUHfoTRd2tPUm1NwwOuZNEHnNw6Um9Z+or0UjETXbqj5wkSP4dTye/R1lpYdr8h0Q8aw4D+RP2e6npZRtGdzWv/pSlcEnzjb484ywk0r8qDl2bMx60LqLzrakTFAu2e8/3TEiV9bauXPev3Vdk13gXXPf4wvR7HS8449QYKdhS+Xrq6rfjBlrjvYQ4ucpJRT68E0RG0BMbvwpySHixcK2I6Sooj0wHhtKGX1qEtNLGbI7Jv/GWQ4QnOSvFZX97sd4q0v6s4mOHPMsd8jQ3owg55+BESoaF/faFAXNuFyXP7UIvIEX7VvQdjMsy5Scsob7d7GbDmvn1yyIEQeIt5vaPmnvkamUfCvAxvu06dB1jqp1MoU5pCYsh1AHyQVFtA1Qp2eNpE6BtmhhYHEUfTER8z06vgz8GqnwyPoi38NkdzSsTJa9/QqRHflZOd97vmBdeD0CQv2Djj3gPTtRrAA3FjADiju2Jl1W8QPDyw2HdMpLD7AnjBiBBFM0IYBoh8YZFJSXHgd0ZT2IOhyfIsA10Oucw0Zy89bxJZwH6Qqc9sWdVFBGQHyI4rY7zXU8fMNqHIHlXiqRjciWn+NetN18BLQHdUEgyE5aQpdXOvElsw2EkXdGDxeDVCanSSzqlby8erGUh1Wr8+VnaG3L3UlakNBK76DmrDAlZRZl67rNTJwC7o= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199021)(40470700004)(46966006)(36840700001)(6916009)(8676002)(316002)(54906003)(70586007)(70206006)(478600001)(426003)(82740400003)(186003)(36756003)(26005)(1076003)(40460700003)(47076005)(336012)(81166007)(82310400005)(7406005)(16526019)(356005)(4326008)(2906002)(41300700001)(6666004)(8936002)(36860700001)(40480700001)(5660300002)(7416002)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:47:09.5508 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfa20993-3530-46d4-acbb-08db39f3fd85 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8724 X-Spam-Status: No, score=0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762816551871322880?= X-GMAIL-MSGID: =?utf-8?q?1762816551871322880?= The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- v9 changes: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 64b6a460d739..ad82d2ab3442 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -90,6 +91,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -1004,6 +1006,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1734,6 +1743,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } };