On Mon, Apr 10 2023 at 01:14, Xin Li wrote:
> From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
>
> FRED inherits the Intel VT-x enhancement of classified events with
> a two-level event dispatch logic. The first-level dispatch is on
> the event type, and the second-level is on the event vector. This
> also means that vectors in different event types are orthogonal,
> thus, vectors 0x10-0x1f become available as hardware interrupts.
>
> Enable interrupt vectors 0x10-0x1f on FRED systems (interrupt 0x80 is
> already enabled.) Most of these changes are about removing the
> assumption that the lowest-priority vector is hard-wired to 0x20.
I'm not really interested in this again premature optimization.
Can we please clarify how the final result of FRED vector layout will
look like?
I rather give up on reclaiming these 16 vectors than making _all_ system
vectors dynamically assignable to avoid an extra partitioning of the
vector space.
Thanks,
tglx
On 6/5/23 07:06, Thomas Gleixner wrote:
> On Mon, Apr 10 2023 at 01:14, Xin Li wrote:
>> From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
>>
>> FRED inherits the Intel VT-x enhancement of classified events with
>> a two-level event dispatch logic. The first-level dispatch is on
>> the event type, and the second-level is on the event vector. This
>> also means that vectors in different event types are orthogonal,
>> thus, vectors 0x10-0x1f become available as hardware interrupts.
>>
>> Enable interrupt vectors 0x10-0x1f on FRED systems (interrupt 0x80 is
>> already enabled.) Most of these changes are about removing the
>> assumption that the lowest-priority vector is hard-wired to 0x20.
>
> I'm not really interested in this again premature optimization.
>
> Can we please clarify how the final result of FRED vector layout will
> look like?
>
> I rather give up on reclaiming these 16 vectors than making _all_ system
> vectors dynamically assignable to avoid an extra partitioning of the
> vector space.
>
So this patch was meant to go *after* the FRED patch set proper.
This patch does not change any of the system vectors except, by
necessity, IRQ_MOVE_CLEANUP_VECTOR, nor does it change the way they are
assigned to fixed vectors today.
It does make the lowest *non*-system vector a variable, but the system
vectors are at the end.
This is something that should be commented: the setting of bits in
system_vector is really misleading: those aren't "system vectors", they
are the vectors reserved for hardware use. On IDT, this means vectors
0-31 because they are used for exceptions, but on FRED interrupts and
exceptions are separate; however vectors 0-15 still need to be reserved
because the APIC doesn't support them.
We *could* change that, but that is completely independent of this.
-hpa
@@ -546,8 +546,8 @@ __visible noinstr void func(struct pt_regs *regs, \
*/
.align IDT_ALIGN
SYM_CODE_START(irq_entries_start)
- vector=FIRST_EXTERNAL_VECTOR
- .rept NR_EXTERNAL_VECTORS
+ vector=FIRST_EXTERNAL_VECTOR_IDT
+ .rept FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR_IDT
UNWIND_HINT_IRET_REGS
0 :
ENDBR
@@ -11,6 +11,11 @@
#include <asm/apicdef.h>
#include <asm/irq_vectors.h>
+/*
+ * The first available IRQ vector
+ */
+extern unsigned int __ro_after_init first_external_vector;
+
/*
* The irq entry code is in the noinstr section and the start/end of
* __irqentry_text is emitted via labels. Make the build fail if
@@ -31,15 +31,23 @@
/*
* IDT vectors usable for external interrupt sources start at 0x20.
- * (0x80 is the syscall vector, 0x30-0x3f are for ISA)
+ * (0x80 is the syscall vector, 0x30-0x3f are for ISA).
+ *
+ * With FRED we can also use 0x10-0x1f even though those overlap
+ * exception vectors as FRED distinguishes exceptions and interrupts.
+ * Therefore, FIRST_EXTERNAL_VECTOR is no longer a constant.
*/
-#define FIRST_EXTERNAL_VECTOR 0x20
+#define FIRST_EXTERNAL_VECTOR_IDT 0x20
+#define FIRST_EXTERNAL_VECTOR_FRED 0x10
+#define FIRST_EXTERNAL_VECTOR first_external_vector
/*
* Reserve the lowest usable vector (and hence lowest priority) 0x20 for
* triggering cleanup after irq migration. 0x21-0x2f will still be used
* for device interrupts.
*/
+#define IRQ_MOVE_CLEANUP_VECTOR_IDT FIRST_EXTERNAL_VECTOR_IDT
+#define IRQ_MOVE_CLEANUP_VECTOR_FRED FIRST_EXTERNAL_VECTOR_FRED
#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
#define IA32_SYSCALL_VECTOR 0x80
@@ -48,7 +56,7 @@
* Vectors 0x30-0x3f are used for ISA interrupts.
* round up to the next 16-vector boundary
*/
-#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)
+#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR_IDT + 16) & ~15) + irq)
/*
* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
@@ -114,7 +122,6 @@
#define FIRST_SYSTEM_VECTOR NR_VECTORS
#endif
-#define NR_EXTERNAL_VECTORS (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
#define NR_SYSTEM_VECTORS (NR_VECTORS - FIRST_SYSTEM_VECTOR)
/*
@@ -1621,12 +1621,17 @@ static void setup_local_APIC(void)
/*
* Set Task Priority to 'accept all except vectors 0-31'. An APIC
* vector in the 16-31 range could be delivered if TPR == 0, but we
- * would think it's an exception and terrible things will happen. We
- * never change this later on.
+ * would think it's an exception and terrible things will happen,
+ * unless we are using FRED in which case interrupts and
+ * exceptions are distinguished by type code.
+ *
+ * We never change this later on.
*/
+ BUG_ON(!first_external_vector);
+
value = apic_read(APIC_TASKPRI);
value &= ~APIC_TPRI_MASK;
- value |= 0x10;
+ value |= (first_external_vector - 0x10) & APIC_TPRI_MASK;
apic_write(APIC_TASKPRI, value);
/* Clear eventually stale ISR/IRR bits */
@@ -46,6 +46,7 @@ static struct irq_matrix *vector_matrix;
#ifdef CONFIG_SMP
static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
#endif
+unsigned int first_external_vector = FIRST_EXTERNAL_VECTOR_IDT;
void lock_vector_lock(void)
{
@@ -796,7 +797,12 @@ int __init arch_early_irq_init(void)
* Allocate the vector matrix allocator data structure and limit the
* search area.
*/
- vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
+ if (cpu_feature_enabled(X86_FEATURE_FRED))
+ first_external_vector = FIRST_EXTERNAL_VECTOR_FRED;
+ else
+ first_external_vector = FIRST_EXTERNAL_VECTOR_IDT;
+
+ vector_matrix = irq_alloc_matrix(NR_VECTORS, first_external_vector,
FIRST_SYSTEM_VECTOR);
BUG_ON(!vector_matrix);
@@ -56,7 +56,7 @@ void __init fred_setup_apic(void)
{
int i;
- for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++)
+ for (i = 0; i < FIRST_EXTERNAL_VECTOR_FRED; i++)
set_bit(i, system_vectors);
/*
@@ -65,7 +65,7 @@ void __init fred_setup_apic(void)
* /proc/interrupts.
*/
#ifdef CONFIG_SMP
- set_bit(IRQ_MOVE_CLEANUP_VECTOR, system_vectors);
+ set_bit(IRQ_MOVE_CLEANUP_VECTOR_FRED, system_vectors);
#endif
for (i = 0; i < NR_SYSTEM_VECTORS; i++) {
@@ -131,7 +131,7 @@ static const __initconst struct idt_data apic_idts[] = {
INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi),
INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function),
INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single),
- INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup),
+ INTG(IRQ_MOVE_CLEANUP_VECTOR_IDT, asm_sysvec_irq_move_cleanup),
INTG(REBOOT_VECTOR, asm_sysvec_reboot),
#endif
@@ -274,13 +274,13 @@ static void __init idt_map_in_cea(void)
*/
void __init idt_setup_apic_and_irq_gates(void)
{
- int i = FIRST_EXTERNAL_VECTOR;
+ int i = FIRST_EXTERNAL_VECTOR_IDT;
void *entry;
idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) {
- entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR);
+ entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR_IDT);
set_intr_gate(i, entry);
}
@@ -359,7 +359,7 @@ void fixup_irqs(void)
* vector_lock because the cpu is already marked !online, so
* nothing else will touch it.
*/
- for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
+ for (vector = first_external_vector; vector < NR_VECTORS; vector++) {
if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
continue;
@@ -1489,6 +1489,8 @@ DEFINE_IDTENTRY_IRQ(spurious_interrupt)
pr_info("Spurious interrupt (vector 0x%x) on CPU#%d, should never happen.\n",
vector, smp_processor_id());
}
+
+unsigned int first_external_vector = FIRST_EXTERNAL_VECTOR_IDT;
#endif
static void dispatch_table_spurious_interrupt(struct pt_regs *regs)