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[2620:137:e000::1:20]) by mx.google.com with ESMTP id qf9-20020a1709077f0900b0091fca6007bbsi6022434ejc.488.2023.04.09.20.19.47; Sun, 09 Apr 2023 20:20:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229718AbjDJDRV (ORCPT + 99 others); Sun, 9 Apr 2023 23:17:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229512AbjDJDRP (ORCPT ); Sun, 9 Apr 2023 23:17:15 -0400 Received: from out30-111.freemail.mail.aliyun.com (out30-111.freemail.mail.aliyun.com [115.124.30.111]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E5F72D79; Sun, 9 Apr 2023 20:17:14 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R231e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046049;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0VfeyoDh_1681096629; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VfeyoDh_1681096629) by smtp.aliyun-inc.com; Mon, 10 Apr 2023 11:17:10 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v2 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Date: Mon, 10 Apr 2023 11:17:00 +0800 Message-Id: <20230410031702.68355-2-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-8.0 required=5.0 tests=ENV_AND_HDR_SPF_MATCH, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748852362839375631?= X-GMAIL-MSGID: =?utf-8?q?1762757769199309108?= Alibaba's T-Head Yitan 710 SoC is built on Synopsys' widely deployed and silicon-proven DesignWare Core PCIe controller which implements PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue --- .../admin-guide/perf/dwc_pcie_pmu.rst | 61 +++++++++++++++++++ Documentation/admin-guide/perf/index.rst | 1 + 2 files changed, 62 insertions(+) create mode 100644 Documentation/admin-guide/perf/dwc_pcie_pmu.rst diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst new file mode 100644 index 000000000000..0672e959ebe4 --- /dev/null +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst @@ -0,0 +1,61 @@ +====================================================================== +Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU) +====================================================================== + +DesignWare Cores (DWC) PCIe PMU +=============================== + +To facilitate collection of statistics, Synopsys DesignWare Cores PCIe +controller provides the following two features: + +- Time Based Analysis (RX/TX data throughput and time spent in each + low-power LTSSM state) +- Lane Event counters (Error and Non-Error for lanes) + +The PMU is not a PCIe Root Complex integrated End Point (RCiEP) device but +only register counters provided by each PCIe Root Port. + +Time Based Analysis +------------------- + +Using this feature you can obtain information regarding RX/TX data +throughput and time spent in each low-power LTSSM state by the controller. + +The counters are 64-bit width and measure data in two categories, + +- percentage of time does the controller stay in LTSSM state in a + configurable duration. The measurement range of each Event in Group#0. +- amount of data processed (Units of 16 bytes). The measurement range of + each Event in Group#1. + +Lane Event counters +------------------- + +Using this feature you can obtain Error and Non-Error information in +specific lane by the controller. + +The counters are 32-bit width and the measured event is select by: + +- Group i +- Event j within the Group i +- and Lane k + +Some of the event counters only exist for specific configurations. + +DesignWare Cores (DWC) PCIe PMU Driver +======================================= + +This driver add PMU devices for each PCIe Root Port. And the PMU device is +named based the BDF of Root Port. For example, + + 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) + +the PMU device name for this Root Port is dwc_rootport_3018. + +Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: + + $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ + +average RX bandwidth can be calculated like this: + + PCIe TX Bandwidth = PCIE_TX_DATA * 16B / Measure_Time_Window diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst index 9de64a40adab..11a80cd28a2e 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -19,5 +19,6 @@ Performance monitor support arm_dsu_pmu thunderx2-pmu alibaba_pmu + dwc_pcie_pmu nvidia-pmu meson-ddr-pmu