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[83.9.1.37]) by smtp.gmail.com with ESMTPSA id h2-20020a2e3a02000000b002a618eb72b1sm811031lja.98.2023.04.07.06.28.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 06:28:38 -0700 (PDT) From: Konrad Dybcio Date: Fri, 07 Apr 2023 15:28:34 +0200 Subject: [PATCH 4/6] arm64: dts: qcom: sc7280: Fix up the gic node MIME-Version: 1.0 Message-Id: <20230407-topic-msm_dtb-v1-4-6efb4196f51f@linaro.org> References: <20230407-topic-msm_dtb-v1-0-6efb4196f51f@linaro.org> In-Reply-To: <20230407-topic-msm_dtb-v1-0-6efb4196f51f@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Greg Kroah-Hartman , Wesley Cheng , Stanimir Varbanov , Vikash Garodia , Mauro Carvalho Chehab , Mathieu Poirier , Manivannan Sadhasivam Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Stanimir Varbanov , linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680874110; l=1494; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gHkzosUqi4bzAs9dpyelWGTDvy9GQH7llzRSHl6mEos=; b=vqvoGg7o3fTzGx7vo2BEYDCXp5lvFkui2hVK5Zlj/spa9/z9GyvocahhSArwYxz23Agovl07UXC+ zft2HNhADd3ZtyJKEv7cFmxO2Z6+RnmniJonP8w9Z7VA7RmgPy76 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762524356186346286?= X-GMAIL-MSGID: =?utf-8?q?1762524356186346286?= Fix the following schema warning: gic-its@17a40000: False schema does not allow {'compatible': ['arm,gic-v3-its'], 'msi-controller': True, '#msi-cells': [[1]], 'reg': [[0, 396623872, 0, 131072]], 'status': ['disabled']} And reorder the properties to be more in order with all other nodes. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0cdb16316021..3292b046a8d3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5182,20 +5182,20 @@ apps_smmu: iommu@15000000 { intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; reg = <0 0x17a00000 0 0x10000>, /* GICD */ <0 0x17a60000 0 0x100000>; /* GICR * 8 */ interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <2>; + #size-cells = <2>; + ranges; - gic-its@17a40000 { + msi-controller@17a40000 { compatible = "arm,gic-v3-its"; + reg = <0 0x17a40000 0 0x20000>; msi-controller; #msi-cells = <1>; - reg = <0 0x17a40000 0 0x20000>; status = "disabled"; }; };