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From: Devi Priya <quic_devipriy@quicinc.com>
To: <agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <lgirdwood@gmail.com>,
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Subject: [PATCH V3 5/5] arm64: dts: qcom: ipq9574: Add cpufreq support
Date: Thu, 6 Apr 2023 12:30:32 +0530
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| Series |
Add regulator support for IPQ9574 SoC
|
|
Commit Message
Devi Priya
April 6, 2023, 7 a.m. UTC
Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz. Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- Changes in V3: - No change arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)
Comments
On 6.04.2023 09:00, Devi Priya wrote: > Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz. > > Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > Changes in V3: > - No change > > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 1f9b7529e7ed..cfef87b5fd22 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -6,6 +6,7 @@ > * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > */ > > +#include <dt-bindings/clock/qcom,apss-ipq.h> > #include <dt-bindings/clock/qcom,ipq9574-gcc.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/reset/qcom,ipq9574-gcc.h> > @@ -37,6 +38,10 @@ > reg = <0x0>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > + clock-names = "cpu"; > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&ipq9574_s1>; > }; > > CPU1: cpu@1 { > @@ -45,6 +50,10 @@ > reg = <0x1>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > + clock-names = "cpu"; > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&ipq9574_s1>; > }; > > CPU2: cpu@2 { > @@ -53,6 +62,10 @@ > reg = <0x2>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > + clock-names = "cpu"; > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&ipq9574_s1>; > }; > > CPU3: cpu@3 { > @@ -61,6 +74,10 @@ > reg = <0x3>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; > + clock-names = "cpu"; > + operating-points-v2 = <&cpu_opp_table>; > + cpu-supply = <&ipq9574_s1>; > }; > > L2_0: l2-cache { > @@ -75,6 +92,47 @@ > reg = <0x0 0x40000000 0x0 0x0>; > }; > > + cpu_opp_table: opp-table-cpu { This is not sorted properly. It should probably come after memory alphabetically ('o' > 'm') Konrad > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-936000000 { > + opp-hz = /bits/ 64 <936000000>; > + opp-microvolt = <725000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1104000000 { > + opp-hz = /bits/ 64 <1104000000>; > + opp-microvolt = <787500>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1416000000 { > + opp-hz = /bits/ 64 <1416000000>; > + opp-microvolt = <862500>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1488000000 { > + opp-hz = /bits/ 64 <1488000000>; > + opp-microvolt = <925000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1800000000 { > + opp-hz = /bits/ 64 <1800000000>; > + opp-microvolt = <987500>; > + clock-latency-ns = <200000>; > + }; > + > + opp-2208000000 { > + opp-hz = /bits/ 64 <2208000000>; > + opp-microvolt = <1062500>; > + clock-latency-ns = <200000>; > + }; > + }; > + > firmware { > scm { > compatible = "qcom,scm-ipq9574", "qcom,scm";
On 4/7/2023 1:21 AM, Konrad Dybcio wrote: > > > On 6.04.2023 09:00, Devi Priya wrote: >> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz. >> >> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> Changes in V3: >> - No change >> >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++ >> 1 file changed, 58 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 1f9b7529e7ed..cfef87b5fd22 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -6,6 +6,7 @@ >> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> +#include <dt-bindings/clock/qcom,apss-ipq.h> >> #include <dt-bindings/clock/qcom,ipq9574-gcc.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> >> @@ -37,6 +38,10 @@ >> reg = <0x0>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >> + clock-names = "cpu"; >> + operating-points-v2 = <&cpu_opp_table>; >> + cpu-supply = <&ipq9574_s1>; >> }; >> >> CPU1: cpu@1 { >> @@ -45,6 +50,10 @@ >> reg = <0x1>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >> + clock-names = "cpu"; >> + operating-points-v2 = <&cpu_opp_table>; >> + cpu-supply = <&ipq9574_s1>; >> }; >> >> CPU2: cpu@2 { >> @@ -53,6 +62,10 @@ >> reg = <0x2>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >> + clock-names = "cpu"; >> + operating-points-v2 = <&cpu_opp_table>; >> + cpu-supply = <&ipq9574_s1>; >> }; >> >> CPU3: cpu@3 { >> @@ -61,6 +74,10 @@ >> reg = <0x3>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >> + clock-names = "cpu"; >> + operating-points-v2 = <&cpu_opp_table>; >> + cpu-supply = <&ipq9574_s1>; >> }; >> >> L2_0: l2-cache { >> @@ -75,6 +92,47 @@ >> reg = <0x0 0x40000000 0x0 0x0>; >> }; >> >> + cpu_opp_table: opp-table-cpu { > This is not sorted properly. It should probably come > after memory alphabetically ('o' > 'm') > Yes, But I see that opp-table-cpu node is already placed after memory@40000000 > Konrad >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp-936000000 { >> + opp-hz = /bits/ 64 <936000000>; >> + opp-microvolt = <725000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1104000000 { >> + opp-hz = /bits/ 64 <1104000000>; >> + opp-microvolt = <787500>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1416000000 { >> + opp-hz = /bits/ 64 <1416000000>; >> + opp-microvolt = <862500>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1488000000 { >> + opp-hz = /bits/ 64 <1488000000>; >> + opp-microvolt = <925000>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-1800000000 { >> + opp-hz = /bits/ 64 <1800000000>; >> + opp-microvolt = <987500>; >> + clock-latency-ns = <200000>; >> + }; >> + >> + opp-2208000000 { >> + opp-hz = /bits/ 64 <2208000000>; >> + opp-microvolt = <1062500>; >> + clock-latency-ns = <200000>; >> + }; >> + }; >> + >> firmware { >> scm { >> compatible = "qcom,scm-ipq9574", "qcom,scm"; Best Regards, Devi Priya
On 7.04.2023 06:53, Devi Priya wrote: > > > On 4/7/2023 1:21 AM, Konrad Dybcio wrote: >> >> >> On 6.04.2023 09:00, Devi Priya wrote: >>> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz. >>> >>> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> >>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >>> --- >>> Changes in V3: >>> - No change >>> >>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++ >>> 1 file changed, 58 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>> index 1f9b7529e7ed..cfef87b5fd22 100644 >>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>> @@ -6,6 +6,7 @@ >>> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. >>> */ >>> +#include <dt-bindings/clock/qcom,apss-ipq.h> >>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h> >>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> >>> @@ -37,6 +38,10 @@ >>> reg = <0x0>; >>> enable-method = "psci"; >>> next-level-cache = <&L2_0>; >>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >>> + clock-names = "cpu"; >>> + operating-points-v2 = <&cpu_opp_table>; >>> + cpu-supply = <&ipq9574_s1>; >>> }; >>> CPU1: cpu@1 { >>> @@ -45,6 +50,10 @@ >>> reg = <0x1>; >>> enable-method = "psci"; >>> next-level-cache = <&L2_0>; >>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >>> + clock-names = "cpu"; >>> + operating-points-v2 = <&cpu_opp_table>; >>> + cpu-supply = <&ipq9574_s1>; >>> }; >>> CPU2: cpu@2 { >>> @@ -53,6 +62,10 @@ >>> reg = <0x2>; >>> enable-method = "psci"; >>> next-level-cache = <&L2_0>; >>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >>> + clock-names = "cpu"; >>> + operating-points-v2 = <&cpu_opp_table>; >>> + cpu-supply = <&ipq9574_s1>; >>> }; >>> CPU3: cpu@3 { >>> @@ -61,6 +74,10 @@ >>> reg = <0x3>; >>> enable-method = "psci"; >>> next-level-cache = <&L2_0>; >>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >>> + clock-names = "cpu"; >>> + operating-points-v2 = <&cpu_opp_table>; >>> + cpu-supply = <&ipq9574_s1>; >>> }; >>> L2_0: l2-cache { >>> @@ -75,6 +92,47 @@ >>> reg = <0x0 0x40000000 0x0 0x0>; >>> }; >>> + cpu_opp_table: opp-table-cpu { >> This is not sorted properly. It should probably come >> after memory alphabetically ('o' > 'm') >> > Yes, But I see that opp-table-cpu node is already placed after > memory@40000000 Oh you're right, the diff doesn't really show that very well and I didn't notice.. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad >> Konrad >>> + compatible = "operating-points-v2"; >>> + opp-shared; >>> + >>> + opp-936000000 { >>> + opp-hz = /bits/ 64 <936000000>; >>> + opp-microvolt = <725000>; >>> + clock-latency-ns = <200000>; >>> + }; >>> + >>> + opp-1104000000 { >>> + opp-hz = /bits/ 64 <1104000000>; >>> + opp-microvolt = <787500>; >>> + clock-latency-ns = <200000>; >>> + }; >>> + >>> + opp-1416000000 { >>> + opp-hz = /bits/ 64 <1416000000>; >>> + opp-microvolt = <862500>; >>> + clock-latency-ns = <200000>; >>> + }; >>> + >>> + opp-1488000000 { >>> + opp-hz = /bits/ 64 <1488000000>; >>> + opp-microvolt = <925000>; >>> + clock-latency-ns = <200000>; >>> + }; >>> + >>> + opp-1800000000 { >>> + opp-hz = /bits/ 64 <1800000000>; >>> + opp-microvolt = <987500>; >>> + clock-latency-ns = <200000>; >>> + }; >>> + >>> + opp-2208000000 { >>> + opp-hz = /bits/ 64 <2208000000>; >>> + opp-microvolt = <1062500>; >>> + clock-latency-ns = <200000>; >>> + }; >>> + }; >>> + >>> firmware { >>> scm { >>> compatible = "qcom,scm-ipq9574", "qcom,scm"; > Best Regards, > Devi Priya
On 4/7/2023 5:29 PM, Konrad Dybcio wrote: > > > On 7.04.2023 06:53, Devi Priya wrote: >> >> >> On 4/7/2023 1:21 AM, Konrad Dybcio wrote: >>> >>> >>> On 6.04.2023 09:00, Devi Priya wrote: >>>> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz. >>>> >>>> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> >>>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >>>> --- >>>> Changes in V3: >>>> - No change >>>> >>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++ >>>> 1 file changed, 58 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>>> index 1f9b7529e7ed..cfef87b5fd22 100644 >>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>>> @@ -6,6 +6,7 @@ >>>> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. >>>> */ >>>> +#include <dt-bindings/clock/qcom,apss-ipq.h> >>>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h> >>>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> >>>> @@ -37,6 +38,10 @@ >>>> reg = <0x0>; >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_0>; >>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >>>> + clock-names = "cpu"; >>>> + operating-points-v2 = <&cpu_opp_table>; >>>> + cpu-supply = <&ipq9574_s1>; >>>> }; >>>> CPU1: cpu@1 { >>>> @@ -45,6 +50,10 @@ >>>> reg = <0x1>; >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_0>; >>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >>>> + clock-names = "cpu"; >>>> + operating-points-v2 = <&cpu_opp_table>; >>>> + cpu-supply = <&ipq9574_s1>; >>>> }; >>>> CPU2: cpu@2 { >>>> @@ -53,6 +62,10 @@ >>>> reg = <0x2>; >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_0>; >>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >>>> + clock-names = "cpu"; >>>> + operating-points-v2 = <&cpu_opp_table>; >>>> + cpu-supply = <&ipq9574_s1>; >>>> }; >>>> CPU3: cpu@3 { >>>> @@ -61,6 +74,10 @@ >>>> reg = <0x3>; >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_0>; >>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >>>> + clock-names = "cpu"; >>>> + operating-points-v2 = <&cpu_opp_table>; >>>> + cpu-supply = <&ipq9574_s1>; >>>> }; >>>> L2_0: l2-cache { >>>> @@ -75,6 +92,47 @@ >>>> reg = <0x0 0x40000000 0x0 0x0>; >>>> }; >>>> + cpu_opp_table: opp-table-cpu { >>> This is not sorted properly. It should probably come >>> after memory alphabetically ('o' > 'm') >>> >> Yes, But I see that opp-table-cpu node is already placed after >> memory@40000000 > > Oh you're right, the diff doesn't really show that very > well and I didn't notice.. > > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Sure, thank you! > > Konrad >>> Konrad >>>> + compatible = "operating-points-v2"; >>>> + opp-shared; >>>> + >>>> + opp-936000000 { >>>> + opp-hz = /bits/ 64 <936000000>; >>>> + opp-microvolt = <725000>; >>>> + clock-latency-ns = <200000>; >>>> + }; >>>> + >>>> + opp-1104000000 { >>>> + opp-hz = /bits/ 64 <1104000000>; >>>> + opp-microvolt = <787500>; >>>> + clock-latency-ns = <200000>; >>>> + }; >>>> + >>>> + opp-1416000000 { >>>> + opp-hz = /bits/ 64 <1416000000>; >>>> + opp-microvolt = <862500>; >>>> + clock-latency-ns = <200000>; >>>> + }; >>>> + >>>> + opp-1488000000 { >>>> + opp-hz = /bits/ 64 <1488000000>; >>>> + opp-microvolt = <925000>; >>>> + clock-latency-ns = <200000>; >>>> + }; >>>> + >>>> + opp-1800000000 { >>>> + opp-hz = /bits/ 64 <1800000000>; >>>> + opp-microvolt = <987500>; >>>> + clock-latency-ns = <200000>; >>>> + }; >>>> + >>>> + opp-2208000000 { >>>> + opp-hz = /bits/ 64 <2208000000>; >>>> + opp-microvolt = <1062500>; >>>> + clock-latency-ns = <200000>; >>>> + }; >>>> + }; >>>> + >>>> firmware { >>>> scm { >>>> compatible = "qcom,scm-ipq9574", "qcom,scm"; >> Best Regards, >> Devi Priya
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 1f9b7529e7ed..cfef87b5fd22 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include <dt-bindings/clock/qcom,apss-ipq.h> #include <dt-bindings/clock/qcom,ipq9574-gcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> @@ -37,6 +38,10 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU1: cpu@1 { @@ -45,6 +50,10 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU2: cpu@2 { @@ -53,6 +62,10 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU3: cpu@3 { @@ -61,6 +74,10 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; L2_0: l2-cache { @@ -75,6 +92,47 @@ reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <725000>; + clock-latency-ns = <200000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <787500>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <862500>; + clock-latency-ns = <200000>; + }; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq9574", "qcom,scm";